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**CS8288   CHIPSlite-sx             (82C836/82C641/82C835)          c?
***Notes:...
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**CS4000   WinCHIPS                 (64200/84021/84025)            c92...
**CS4021   ISA/486                  (84021/84025)                  c92...
**CS4031   CHIPSet                  (84031/84035)              5/10/93...
**CS4041/5 CHIPSet                  (84041/84045)              2/10/95...
**CB8291   ELEAT                    [no datasheet]                 c90...
**CB8295   ELEATsx                  [no datasheet]                 c90...
**82C100   IBM PS/2 Model 30/Super XT                                ?...
**82C110   IBM PS/2 Model 30/Super XT                                ?...
**82C235   Single Chip AT (SCAT)                                   c89...
**82C836   Single Chip 386sx (SCATsx)                              <91...
**F8680/A  PC/CHIP Single-Chip PC                                  c93...
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**64200    (Wingine) High Performance 'Windows Engine'         c:Oct91...
**82C206   Integrated Peripheral Controller                        c86...
**82C601/A Single Chip Peripheral Controller                 <08/30/90...
**82C607   Multifunction Controller                             <Jun88...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91
***Info:...
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**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90
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**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
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**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96
***Info:
[no general section in datasheet]

3. Functional Description
3.1 DRAM Controller
3.1.1 DRAM Type
The SiS5571  can support up to  384MBytes (3 banks) of  DRAMs and each
bank could be single or double sided 64 bits FP (Fast Page mode) DRAM,
EDO  (Extended  Data  Output)   DRAM,  and  SDRAM  (Synchronous  DRAM)
DRAM. Half populated bank(32-bit) is also supported.

The installed DRAM type can be 256K,  512k, 1M, 2M, 4M or 16M bit deep
by n bit  wide DRAMs, and both symmetrical  and asymmetrical type DRAM
are supported. It is also  permissible to mix the DRAMs (FP/EDO/SDRAM)
bank  by bank  and  the  corresponding DRAM  timing  will be  switched
automatically according to register settings.

3.1.2 DRAM Configuration

The SiS5571 can support single  sided or double sided DRAM modules for
each bank. The basic configurations are shown as the following:

3.1.3 Double-sided DRAM    [omitted see datasheet]
3.1.4 Single-sided DRAM    [omitted see datasheet]
3.1.5 DRAM Scramble Table  [omitted see datasheet]
3.1.6 64-bit mapping table [omitted see datasheet]

3.2 DRAM Performance       [omitted see datasheet]

3.3 CPU to DRAM Posted Write FIFOs

There is  a built-in CPU  to Memory posted  write buffer with  8 QWord
deep ( CTMFF). All the write  access to DRAM will be buffered. For the
CPU read miss / Line fill cycles, the write- back data from the second
level cache will be buffered first,  and right after the data had been
posted write into the FIFO, CPU can performs the read operation by the
memory controller starting to read  data from DRAMs. The buffered data
are  then written  to DRAM  whenever no  any other  read  DRAM request
comes. With  this concurrent write  back policy, many wait  states are
eliminated. If  there comes a  bunch of continuous DRAM  write cycles,
some ones will be pending if the CTMFF is full.

3.4 32-bit (Half-Populated) DRAM Access
For the read  access, there will be either single  or burst read cycle
to access the DRAM which depends  on the cacheability of the cycle. If
the  current  DRAM  configuration  is half-populated  bank,  then  the
SiS5571 will assert 8 consecutive  cycles to access DRAM for the burst
cycle.  For the  single cycle that only accesses  DRAM within a DWord,
the SiS5571 will  only issue one cycle to access  DRAM. For the single
cycle that  accesses one  Qword or cross  DWord boundary,  the SiS5571
will issue two consecutive cycles to access DRAM.

3.5 Arbiter
The arbiter is the interface  between the DRAM controller and the host
which  can  access  DRAMs.  In  addition  to  pass  or  translate  the
information  from   outside  to  DRAM  controller,   arbiter  is  also
responsible for which master has  higher priority to access DRAMs. The
arbiter treats different DRAM access  request as DRAM master, and that
makes there be  5 masters which are trying to  access DRAMs by sending
their request to the arbiter. After one of them get the grant from the
arbiter, it owns DRAM bus and begins to do memory data transaction.

The masters are: CPU read request, PCI master, Posted write FIFO write
request, and Refresh  request. The order of these  masters shown above
also stands for their priority to access memory.

3.6 Refresh cycle
The refresh cycle  will occur every 15.6 us. It is  timed by a counter
of 14Mhz input.  The CAS[7:0]# will be asserted at  the same time, and
the RAS[5:0]# are asserted sequentially.

3.7 PCI bridge
SiS5571 is  able to operate  at both asynchronous and  synchronous PCI
clocks. Synchronous  mode is provided for those  synchronous system to
improve the overall system performance.  While in the PCI master write
cycles, post-write  is always performed.  And function  of Write Merge
with CPU-to-DRAM  post-write buffer  is incorporated to  eliminate the
penalty of snooping write-back. On the other hand, prefetch is enabled
for master read cycles by default, and such function could be disabled
optionally.  And, Direct-Read  from CPU-to-DRAM  post-write  buffer is
implemented to eliminate the overhead of snooping write-back also.  In
addition to  Write-Merge and  Direct-Read, Snoop-Ahead also  hides the
overhead of inquiry cycles for master to main memory cycles. These key
functions,  Write-Merge,  Direct-Read  and  Snoop-Ahead,  achieve  the
purpose  of zero  wait for  PCI  burst transfer.   The post-write  and
prefetch buffers are both 16 Double-Word deep FIFOs.

3.8  Snooping Control                          [omitted see datasheet]
3.9  AHOLD/BOFF# Process and Arbiter Interface [omitted see datasheet]
3.10 Target Initiated Termination    	       [omitted see datasheet]
3.11 DATA Flow	      			       [omitted see datasheet]
3.12 PCI Master Read/Write DRAM Cycle	       [omitted see datasheet]


***Configurations:...
***Features:...
**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
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