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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96
***Info:...
***Configurations:...
***Features:...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98
***Info:...
***Configurations:...
***Features:...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
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**W83759/A/F/AF Advanced VL-IDE Disk Controller <96
***Notes:...
***Info:...
***Versions:...
***Features:...
**W83769 Local Bus IDE Solution <94
***Info:
GENERAL DESCRIPTION
The W83769 is a high-performance, low-cost, highly integrated logic
design for IDE hard disk applications in PCI (Peripheral Component
Interconnect) local bus systems. It provides a bridge between a
standard IDE drive and the PCI local bus. The W83769 is fully
compatible with the ANSI ATA 3.0 specifications for IDE hard disk
operation and the PCI SIG revision 2.0 specifications for the PCI
local bus protocol. Packaged in a 100-pin PQFP, the W83769 directly
supports the 32-bit PCI bus without requiring any external TTLs.
The W83769 operates at up to 50 MHz and provides a full 32-bit data
path to the PCI bus. Doubleword read and write operations are provided
via internal control and conversion logic. Write posting and
read-ahead allows CPU memory cycles to run concurrently with IDE
cycles and improves the hard disk buffer-to-host transfer rate.
The IDE drive interface timing of the W83769 is completely software
programmable, including command active/recovery timing and address
setup-hold timing for each drive. The device supports Fast
ATA/Enhanced IDE mode 3 timing and IORDY monitoring for better
performance. The W83769 directly supports four IDE drives with
170/1F0 dual IDE connectors. The IO base addresses of the
primary/secondary IDE connector are exchangeable by power-on strap
option.
***Versions:...
***Features:...
**
**UARTS:
**W86C250A UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
**Other:...
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