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**440 series:
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
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**450NX (?) 06/29/98:...
**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
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**UM82C088 PC/XT Integration Chip <91
***Info:...
***Configurations:...
***Features:...
**UM82C230 286AT MORTAR Chip Set <91...
**UM82C210 386SX/286 AT Chip Set <91...
**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?...
**UM82C380 386 HEAT PC/AT Chip Set <91...
**UM82C480 386/486 PC Chip Set c91...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
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*Western Digital...
**WD7625 Desktop Buffer Manager <10/01/92
***Info:
INTRODUCTION
This document describes the two separate functions, Address Buffer and
Data Buffer, available in the WD7625LV chip. A strapping input pin
selects the Data Buffer Function when strapped low, otherwise it
selects the Address Buffer Function.
GENERAL DESCRIPTION
The WD7625LV is a combination design which includes two separate
functions: Address Buffer and Data Buffer in one chip. A strapping
input pin selects the Data Buffer Function if it is strapped low;
otherwise, it selects the Address Buffer Function. For designs that
use both the data buffer and the address buffer functions, two
WD7625LV devices are needed in the system.
In the Address Buffer Function, the WD7625LV is an address buffer and
power management chip.
In the Data Buffer Function, the WD7625LV is a data buffer, IDE buffer
and I/O register device for the WD7x00 16-bit chip sets.
***Versions:...
***Features:
ADDRESS BUFFER FEATURES
o Allows WD7SC10A, WD7855, WD8110, WD7710, and WD7910 based designs
with WD7620/30 for laptop or notebook systems
o Will work in three different power supply modes:
- 3.3V only
- 5V only
- Mix mode 3.3V and 5V
o Direct connect to AT Address Bus SA1:19 and LA17:23 with 24 mA
drive
o Power Management Control (PMC) input MUX
o General purpose suspend/resume and power supply control logic
o Fifteen-bit Power Management Control (PMC) output register and
control logic
o Low power request and resume signal delay simplify the design of
the power supply
o Watchdog timer for system idle detection
o DRAM WE signal from WD7xc10 inversion and buffering
o RESIN output generation from reset switch (RSTSW)
o System Reset generation
o Chip select decoding for registers in the WD7625LV Data Buffer
Function
o 144-pin SQFP package
DATA BUFFER FEATURES
o Allows WD7SC10A, WD7855, WD7710, and WD7910 based designs with
WD7620/30 for laptop or notebook systems
o Will work in three different power supply modes:
- 3.3V only
- 5V only
- Mix mode 3.3V and 5V
o Direct connection to AT data bus; 20K integrated pull-up for
SD(0:7)
o Direct connection to IDE data bus
o Two general purpose 8-bit I/O registers:
- Register A
- Register B
o One general purpose 8-bit I/O Register C, with single bit
set/reset control
o One general purpose 1-bit I/O Register Y0
o One 4-bit general purpose input only Register Z
o DRQ multiplexing plus 20K integrated pull-down
o DACK demultiplexing
o SMEMR, SMEMW signals plus 22K internal pull-up
o 144-pin SOFP package
**WD8120LV Super I/O [no datasheet] ?
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