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*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset <01/09/95
***Notes:...
***Info:...
***Configurations:...
***Features:...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5120 Pentium PCI/ISA Chipset (Mobile) <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5511/5512/5513 Pentium PCI/ISA <06/14/95...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
**UM82C852 Multi I/O For XT <91
***Info:...
***Versions:...
***Features:...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
*VIA...
*VLSI...
**VL82C110 Combination I/O chip ?
***Info:
The VL82C110 Combination I/O chip replaces several of the commonly
used peripherals found in PC/AT-compatible computers. The VL82C110
contains a 765A compatible floppy disk controller with a digital data
clock separator, writ precompensation logic and the necessary control
registers. It also contains two 16C450 compatible UARTs, a Centronics
compatible printer port, and an internal PMU (power management unit)
which is useful in applications where low power consumption is
essential. Additionally, a PLL clock circuit is included to provide
one of seven of the commonly used CPU clock frequencies. This 100-pin
chip allows designers to implement a very cost-effective, minimum chip
count motherboard containing functions that are common to virtually
all PCs.
The internal PMU provides a Sleep output which OS asserted via
automatically after a programmable time delay period of inactivity in
any of the major on-chip functions. Conversely, the sleep output will
be de-asserted when any activity is detected to any of the major
on-chip functions.
The on-chip UARTs are 100% software compatible with the VL16C450 ACE.
The bidirectional parallel port provides a PS/2 software compatible
interface between a Centronics-style printer and the VL82C110. Direct
drive is provided so that all that is necessary to interface to the
line printer is a resistor-capacitor network. The bidirectional
feature (option) is software programmable for backwards PC/AT-
compatibility.
The on-chip disk controller OS 100% compatible to the industry
standard 765A. The internal digital data separator is capable of
operating up to a 500 kb/s data rate. The Controller also implements
all of the DP8473 disk controller functions.
The necessary signals are provided to implement the Integrated Drive
Electronics (IDE) interface.
A 24 MHz oscillator is included for UART baud rate generation and the
floppy disk controller clock, It is also used to generate, via
software control, a 20, 25, 32, 40, 50, 66 or 80 MHz output which can
be used as a CPU input clock. This feature may be disabled at power-up
reset time.
Software configurable registers are provided to enable and disable
major blocks, assign addresses, and control other functions within the
VL82C110.
***Versions:...
***Features:...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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