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*_IBM...
*ACC Micro...
**ACC5500 Multifunction I/O Control Chip for PS2 Model 50/60 c88
***Info:...
***Versions:...
***Features:...
**
**Other chips...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95
***Notes:...
***Info:...
***Versions:...
***Features:...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**SL9XXX FlexSet family General information
The SL9XXX series seems to have been designed to work with the 80286,
80386SX and 80386DX, and is possibly compatible with the 80486. What-
ever CPU used, the chipset contains the following chips, known as the
"Core AT Logic chips":
SL9011 System Controller
SL9020 Data Controller (2x for 32bit 386DX)
SL9025 Address Controller
SL9030 Integrated Peripheral Controller
The memory controller is then selected based on the CPU. It appears
that the lineup originally consisted of the following chips, known as
"Personalized AT Logic":
SL9151 Page Interleave Memory (80286)
SL9250 Memory Controller (80386SX)
SL9350 Page Mode Memory Controller (80386DX)
Later updates were:
SL9251 Page Interleave Memory Controller (80386SX)
SL9351 Page Interleave Memory Controller (80386DX)
Further updates were:
SL9252 System and Memory Controller (80386SX)
SL9352 System and Memory Controller (80386DX)
As far as i can tell, these chips only require the addition of the
SL9020, or 2x in the case of the SL9352. The datasheets are quite
terse.
These parts and the whole design of the datasheets are very similar to
the chipsets released by Logicstar. I, however, cannot find any record
of a link between the companies. See *Logicstar for details.
**SL9011 System Controller (80286/80386SX/DX, 16/20/25MHz) <Jan90...
**SL9020 Data Controller <Jan90...
**SL9025 Address Controller <Jan90...
**SL9030 Integrated Peripheral Controller <Jan90...
**SL9090/A Universal PC/AT Clock Chip <oct88...
**SL9095 Power Management Unit ?...
**SL9151 80286 Page Interleave Memory Controller (16-25MHz) ?...
**SL9250 80386SX Page Mode Memory Controller (16/20MHz 8MB) ?...
**SL9251 80386SX Page Interleave Memory Controller <04/13/90...
**SL9252 80386SX System and Memory Controller <06/12/90...
**SL9350 80386DX Page Mode Memory Controller (16-25MHz 16MB) ?...
**SL9351 80386DX Page Interleave Memory Controller (33MHz) ?...
**SL9352 80386DX System and Memory Controller <06/12/90...
**SLXXXX Other chips...
**
**VT82C470 "Jupiter", Chip Set (w/o cache) 386 [no datasheet] ?
**VT82C475 "Jupiter", Chip Set (w/cache) 386 [no datasheet] ?
**VT82C486/2/3 "GMC chipset" [no datasheet, some info] ?...
**VT82C495/480 "Venus" Chip Set [no datasheet] ?
**VT82C495/491 ? EISA Chip Set [no datasheet, some info] <93...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94...
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
**Notes:
VLSI was originally known as VTI.
see:
http://www.fundinguniverse.com/company-histories/vlsi-technology-inc-history/
**VL82C*** IBM/INTEL Direct replacement ?...
**VL82CPCAT-QC AT 12 MHz 0/1 ws c88...
**VL82CPCPM-QC AT 16 MHz 0/1 ws [no datasheet] c88...
**VL82CPCAT-16QC/-20QC AT 16 MHz or 20 MHz, 0/1 ws +386SX c89...
**VL82CPCPM-16QC/-20QC AT 16 MHz or 20 MHz, Page-Mode +386SX c89...
**VL82C031/032/033 PS/2 Model 30-compatible chip set c88...
**VL82C286-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?...
**VL82C386-SET TOPCAT 386DX PC/AT-Compatible Chip Set ?...
**VL82C386sx-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?...
**VL82C310 SCAMP-LT ?...
**VL82C311 SCAMP-DT ?...
**VL82C311L SCAMP-DT 286 ?...
**VL82C312 SCAMP Power Management Unit (PMU) ?...
**VL82C315A SCAMP II, Low-Power Notebook Chipset ?...
**VL82C322A SCAMP II, Power Management Unit (PMU) ?...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?
***Info:
The VL82C520 Lynx/M chipset is VLSI's system solution optimized for
the expanding mobile Pentium market. Carrying forward VLSI's mobile
strategy and leveraging successful desktop innovations to offer a
complete solution, Lynx/M leaps forward and integrates the system
controller into a single Ball Grid Array (BGA) package. Included in
the Lynx/M solution is a PCI "Super I/O" controller that integrates
all the standard mobile peripherals. The Lynx/M offers a total
solution compatible with the Common Architecture industry standard
implementing highly efficient DDMA (Distributed DMA), Serial IRQ, and
features for primary PCI hot docking using a Common Architecture
compatible PCI to PCI bridge in the docking station.
Lynx/M System Controller; VL82C521
Packaged in a space-efficient low-profile 352 BGA, the Lynx/M System
Controller is the heart of the solution. BGA packaging allows
integrating functions usually partitioned into multiple packages. the
integrated functions include a 66Mhz CPU interface, 3.3V mobile PCI
2.1 compliant bus controller, 64-bit SDRAM, EDO, and FPM DRAM
controller with nine-deep fast access smart write-buffers, on-board L2
256KB write-back cache controller, and VLSI's WATTSmart power
management control. The DRAM interface provides drive for up to 24
memory devices thereby eliminating the need for external
drivers. Also, selecting SDRAM provides the opportunity to implement a
high performance system without an L2 cache.
Lynx/M Peripheral Controller; VL82C522
The Lynx/M chipset also includes a PCI Super I/O device, the Lynx/M
Mobile Peripheral Controller (MPC). This device, also packaged in a
low-profile 352 BGA, integrates a PCI 2.1 compliant bus interface, a
fully buffered Bus Mastering IDE controller, an '077 floppy disk
controller, Enhanced Capabilities Port (ECP), two 16550 UARTs with
modem functionality, an SMB/I2C bus, an IrDA 1.1 compatible Fast
Infrared communications port with ASK functionality, a Real-Time
Clock, two pulse-width modulator outputs (PWM), and a 33MHz 8052
microcontroller. Two on-board PLLs with buffering provide all the
required system clocks from only two crystal inputs, 14.318MHz and
32KHz.
A sub-ISA bus supporting 8- or 16-bit I/O or DDMA transfers, and ISA
Bus Mastering supports audio devices. Additionally, eight positive PCI
address decodes provide support to Sub-ISA peripherals.
The 8052 provides the keyboard controller functionality with built-in
scan for matrix keyboards and system boot controller functionality to
completely wake up any part or all of the system from any level of
suspend. The wake-up event can be a system event, timer, or any key
depression on the keyboard. The MPC also provides up to 25 GPIO pins
with expansion capabilities to provide flexible control of system
components.
Singular ROM architecture enabled by the integrated 8052 keyboard
controller saves both PCB space and cost by permitting a solitary ROM,
Flash, or SRAM device to be used for keyboard, graphics and system
BIOS.
WATTSMART Power Management
Incorporated in the Lynx/M chipset, the WATTSmart is a System
Management Mode-based power management system. WATTSmart includes
multiple system event monitoring, a watchdog timer, System Management
Interrupt (SMI) generation, multiple I/O traps, CPU Stop Clock
control, and provides three general purpose system Management I/O pins
(SMIOs) for control and monitoring of external devices.
Virtually all activity resources are available as speed up events and
to generate SMIs. SMIs can be generated by activity or after a period
of inactivity. An SMI that is generated from activity is generally for
a powered-down device, and the SMM handler can restore the device to
normal operation. An SMI from activity can also be used to resume the
system, start the clocks, etc.
Background
Lynx/M incorporates functions from previous desktop and mobile
chipsets. Baselinning from proven core system blocks and modifying to
reflect new market requirements allows VLSI to meet the Time-To-Market
expectations while minimizing risk.
Utilizing high-pin count BGA packaging allows Lynx/M to reduce board
space requirements by greater than 45%. this allows room on the PCB
for additional functionality while reducing the complexity of
multi-layer system boards.
Accessing VLSI's internal fab technology allows Lynx/M a path to an
advanced 0.6um CMOS process thereby achieving a true 3.3V system
without performance trade-offs.
***Configurations:...
***Features:...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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