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**What's not included:
All information included in this file can be referenced to some
document or picture. Or at least should be:-) As a result of this,
proprietary chip sets, and odd combinations of different chip sets are
not usually included. There tends to be scant information on
proprietary chip sets, i.e. no datasheet. Similarly chip sets built
using some components from one manufacture and some from another are
kind of difficult to deal with.
An example I know of is a 25 MHz 386 DX motherboard that uses the
Intel N82230/N82231 (formerly, ZyMOS) 286 chip set, with an AUStek
cache Controller. I know it existed but there is no documentation.
So the best I can say you'll have to take my word that it existed. I
can't include it because there is no real information there.
Also not included is anything that isn't a PC-compatible chip
set. I.e. no Macintosh info. Any Information on PC-incompatibles/
pseudo-compatibles, and other weirdi-type stuff I have a particular
interest in. See the section: 'Info needed on'. Some information on
video chip sets is included, occasionally but the focus is on
motherboard implementation.
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95
***Notes:...
***Info:
****General:
The Intel 450KX/GX PCIsets provide a high-performance system solution
for Pentium Pro processor-based PCI systems by combining high
integration, high performance technology with a scalable architecture
that is capable of high throughput for up to four Pentium Pro
processors. Scalability provides a wide range of system solutions from
cost-effective uniprocessor systems to high-end multiprocessor systems
without sacrificing performance. For systems requiring extensive I/O
(e.g., file servers), a second PB can be easily added providing two
high-performance PCI bus structures. The flexibility of the memory
controller permits easy expansion from a simple non-interleaved
organization to a 2-way or 4-way interleaved organization to increase
performance. Extended error checking and logging, ECC, and the ability
to build in redundancy (e.g, multiple processors and dual PCI bridges)
provides a comprehensive solution for systems requiring high
reliability.
The PCIset may contain design defects or errors known as
errata. Current characterized errata are available upon request.
----------------------------------------------------------------------
This document describes both the Intel 450KX and 450GX
PCIsets. Unshaded areas apply to both the PCIsets. Shaded areas,
like this one, describe the 450GX operations that differ from the
450KX.
----------------------------------------------------------------------
1.0 INTEL 450KX PCISET
The 450KX desktop PCIset consists of the 82454KX PCI Bridge (PB) and
the Memory Controller (MC). The MC consists of the 82453KX DRAM
Controller (DC), the 82452KX Data Path (DP), and four 82451KX Memory
Interface Components (MIC). The system configuration using the Intel
450KX PCIset supports one PB, one MC and up to two Pentium Pro
processors (Figure 1) [see datasheet]. An ISA subsystem is also
located below the PB. For Pentium Pro processor bus error detection,
the 450KX generates and checks parity over the address and
request/response signal lines. This feature can be enabled/disabled
during system configuration.
KX PCI Bridge (PB)
The PB is a single-chip host-to-PCI Bridge. A rich set of CPU-to-PCI
and PCI-to-CPU bus transaction translations optimize bus bandwidth and
improve system performance. All ISA and EISA regions are
supported. Three programmable memory gaps can be created—a PCI Frame
Buffer Region with specialized frame buffer attributes and two
general-purpose memory gaps (called the Memory Gap Region and the High
Memory Gap Region).
The PB takes advantage of the Pentium Pro processor ratio clocking
scheme to assure modularity now and upgradability in the future. The
PB has a synchronous interface to the Pentium Pro processor bus and
supports a derived clock for the synchronous PCI interface. The PB
derives either a 30 or 33 MHz PCI clock output from the Pentium Pro
processor bus clock. The PB PCI signals are 5 volt tolerant and can be
used with either 5 volt or 3.3 volt PCI devices.
KX Memory Controller (MC)
The combined MC (DC, DP, and four MICs) act as one physical load on
the Pentium Pro processor bus. The DC provides control for the DRAM
memory subsystem, the DP provides the data path, and the four MICs are
used to interface the MC datapath with the DRAM memory subsystem.
The memory configuration can be either 2-way interleaved or
non-interleaved. Both single-sided and double-sided SIMMs are
supported. DRAM technologies up to 64 Mbits at speeds of 50ns, 60ns,
and 70ns can be used. Asymmetric DRAM is supported up to two bits of
asymmetry (e.g., 12 row address lines and 10 column address
lines). The maximum memory size is 1 Gbyte for the 2-way interleaved
configuration and 512 Mbytes for the non-interleaved configuration
using 16 Mbit technology. In addition to these memory configurations,
the MC provides data integrity features including ECC in the memory
array. These features, as well as a set of error reporting mechanisms,
can be selected via configuration of the MC. Each interleave provides
a 64-bit data path to main memory (72-bits including ECC).
The MC is PC compatible. All ISA and EISA regions are decoded and
shadowed based on programmable configurations. Regions above 1 Mbyte
with size 1 Mbyte or larger that are not mapped to memory may be
reclaimed by setting the appropriate configuration in the MC. Three
programmable memory gaps can be created and are called the Low Memory
Gap Region, the Memory Gap Region and the High Memory Gap Region.
2.0 INTEL 450GX PCISET
The Intel 450GX PCIset includes the features discussed for the Intel
450KX PCIset and provides the additional capabilities described in
this section. This PCIset consists of the 82454GX PCI Bridge (PB) and
the Memory Controller (MC). The MC for the 450GX consists of the
82453GX DRAM Controller (DC), the 82452GX Data Path (DP), and four
82451GX Memory Interface Controllers (MIC). The 450GX permits two PBs
and two MCs in a system. In addition to parity support on the host bus
described for the 450KX, the 450GX generates and checks ECC over the
host data lines. This feature can be enabled/disabled during
configuration.
One aspect of the 450GX is that it can be used as a drop-in
replacement for an 450KX design. Additional pins are added in such a
way that proper wiring of 450KX test pins (GTLHI, TESTLO, and TESTHI)
will allow an 450GX to operate in the same system while functioning
exactly as an 450KX.
GX PCI Bridge (PB)
Two 82454GX PBs can be used in a system. Dual PBs provide a modular
approach to I/O performance improvements. Compatibility versus speed
are addressed with an optional compatibility operating mode to
guarantee standard bus compatible operation when needed, and allow bus
concurrency when possible.
In a dual PB system, one PB is configured by strapping options at
power-up to be the Compatibility PB. This PB provides the PC
compatible path to Boot ROM and the ISA/EISA bus. The second PB is
configured by the strapping options to be the Auxiliary PB. The
Compatibility PB is the highest priority bridge to ensure a proper
response time for ISA bus masters. When two PBs are on the host bus,
the Compatibility PB handles arbitration with an internal arbiter.
GX Memory Controller (MC)
The memory configuration can be either 4-way interleaved, 2-way
interleaved, or non-interleaved. Both single-sided and double-sided
SIMMs are supported. DRAM technologies up to 64Mbit at speeds of 50ns,
60ns, and 70ns can be used. Asymmetric DRAM is supported up to two
bits of asymmetry (e.g., 12 row address lines and 10 column address
lines). The maximum memory size is 4 Gbytes for the 4-way interleaved
configuration, 2 Gbytes for the 2-way interleaved configuration, and 1
Gbyte for the non-interleaved configuration using 64 Mbit
technology. The MC provides a 64-bit data path to main memory (72-bits
including ECC) for each interleave (288 bits for a 4-way interleave
design).
****82454KX/GX PCI Bridge (PB):...
****Memory Controller (MC) 82453KX/GX (DC), 82452KX/GX (DP), 82451KX/GX (MIC)...
***Configurations:...
***Features:...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**Other:
OPTi 82C200 - ChromaCast LCD-VGA chipset
OPTi 82C205 - LCD panel controller / scalar
OPTi 82C264 - 2D VGA controller
OPTi 82C265 - Video ????????????????????????????
OPTi 82C268 - Video ????????????????????????????
OPTi 82C611 - EIDE VLB
OPTi 82C611A - EIDE VLB
OPTi 82C621 - PCI-to-IDE controller
OPTi 82C621A - PCI-to-IDE controller
OPTi 82C824 - FireFox PCI to PCMCIA Controller
OPTi 82C825 - FireBridge II PCI to PCMCIA Controller
OPTi 82C814 - Docking Station Controller for laptops (PCI-to-PCI bridge)
OPTi 82C842 - PCI-to-IEEE 1393 FireWire
OPTi 82C832 - ?????????????????????????????????????????
OPTi 82C861 - PCI-to-USB Bridge c1997
OPTi 82C862 - PCI-to-USB Bridge 4x port
OPTi 82C863 - PCI-to-USB Bridge 2x port
OPTi 82C871 - PCI-to-USB Bridge + Sound Blaster compatibility and USB 2.0
OPTi 82C916 - Audio, ISA, serial CODEC) used in combination with Vendetta chipset 82C750
OPTi 82C924 - Audio, ISA
OPTi 82C925 - ISA Audio Controller (replaces the 924)
OPTi 82C928 - (MAD16) ISA Audio Controller (Emulates Sound Blaster Pro) c1993
OPTi 82C929 - (MAD16 Pro) ISA Audio Controller (Emulates Sound Blaster Pro) c1994
OPTi 82C930 - ISA Audio Controller (Emulates Sound Blaster Pro, AdLib)
OPTi 82C931 - ISA Audio controller (Emulates Sound Blaster Pro, AdLib)
OPTi 82C933 - Audio ?????????????????????????????
OPTi 82C935 - EV1935 ECTIVA MachOne PCI Audio
OPTi 82C941 - Wavetable chip, has something to do with 82C930
OPTi 82C950 - (MAD32) Audio/Modem controller (Emulates Sound Blaster Pro) c1994
OPTi 92C160 - Clock Generator for 92C168
OPTi 92C168 - LCD VGA controller c1993
OPTi 92C178 - LCD VGA controller with blt c1993
OPTi 92C264 - 2D VGA controller
-------------------------------------------------
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C311 SCAMP-DT ?
***Info:...
***Configurations:...
***Features:...
**VL82C311L SCAMP-DT 286 ?...
**VL82C312 SCAMP Power Management Unit (PMU) ?...
**VL82C315A SCAMP II, Low-Power Notebook Chipset ?...
**VL82C322A SCAMP II, Power Management Unit (PMU) ?...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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