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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96
***Info:
[no general section in datasheet]
3. Functional Description
3.1 DRAM Controller
3.1.1 DRAM Type
The SiS5571 can support up to 384MBytes (3 banks) of DRAMs and each
bank could be single or double sided 64 bits FP (Fast Page mode) DRAM,
EDO (Extended Data Output) DRAM, and SDRAM (Synchronous DRAM)
DRAM. Half populated bank(32-bit) is also supported.
The installed DRAM type can be 256K, 512k, 1M, 2M, 4M or 16M bit deep
by n bit wide DRAMs, and both symmetrical and asymmetrical type DRAM
are supported. It is also permissible to mix the DRAMs (FP/EDO/SDRAM)
bank by bank and the corresponding DRAM timing will be switched
automatically according to register settings.
3.1.2 DRAM Configuration
The SiS5571 can support single sided or double sided DRAM modules for
each bank. The basic configurations are shown as the following:
3.1.3 Double-sided DRAM [omitted see datasheet]
3.1.4 Single-sided DRAM [omitted see datasheet]
3.1.5 DRAM Scramble Table [omitted see datasheet]
3.1.6 64-bit mapping table [omitted see datasheet]
3.2 DRAM Performance [omitted see datasheet]
3.3 CPU to DRAM Posted Write FIFOs
There is a built-in CPU to Memory posted write buffer with 8 QWord
deep ( CTMFF). All the write access to DRAM will be buffered. For the
CPU read miss / Line fill cycles, the write- back data from the second
level cache will be buffered first, and right after the data had been
posted write into the FIFO, CPU can performs the read operation by the
memory controller starting to read data from DRAMs. The buffered data
are then written to DRAM whenever no any other read DRAM request
comes. With this concurrent write back policy, many wait states are
eliminated. If there comes a bunch of continuous DRAM write cycles,
some ones will be pending if the CTMFF is full.
3.4 32-bit (Half-Populated) DRAM Access
For the read access, there will be either single or burst read cycle
to access the DRAM which depends on the cacheability of the cycle. If
the current DRAM configuration is half-populated bank, then the
SiS5571 will assert 8 consecutive cycles to access DRAM for the burst
cycle. For the single cycle that only accesses DRAM within a DWord,
the SiS5571 will only issue one cycle to access DRAM. For the single
cycle that accesses one Qword or cross DWord boundary, the SiS5571
will issue two consecutive cycles to access DRAM.
3.5 Arbiter
The arbiter is the interface between the DRAM controller and the host
which can access DRAMs. In addition to pass or translate the
information from outside to DRAM controller, arbiter is also
responsible for which master has higher priority to access DRAMs. The
arbiter treats different DRAM access request as DRAM master, and that
makes there be 5 masters which are trying to access DRAMs by sending
their request to the arbiter. After one of them get the grant from the
arbiter, it owns DRAM bus and begins to do memory data transaction.
The masters are: CPU read request, PCI master, Posted write FIFO write
request, and Refresh request. The order of these masters shown above
also stands for their priority to access memory.
3.6 Refresh cycle
The refresh cycle will occur every 15.6 us. It is timed by a counter
of 14Mhz input. The CAS[7:0]# will be asserted at the same time, and
the RAS[5:0]# are asserted sequentially.
3.7 PCI bridge
SiS5571 is able to operate at both asynchronous and synchronous PCI
clocks. Synchronous mode is provided for those synchronous system to
improve the overall system performance. While in the PCI master write
cycles, post-write is always performed. And function of Write Merge
with CPU-to-DRAM post-write buffer is incorporated to eliminate the
penalty of snooping write-back. On the other hand, prefetch is enabled
for master read cycles by default, and such function could be disabled
optionally. And, Direct-Read from CPU-to-DRAM post-write buffer is
implemented to eliminate the overhead of snooping write-back also. In
addition to Write-Merge and Direct-Read, Snoop-Ahead also hides the
overhead of inquiry cycles for master to main memory cycles. These key
functions, Write-Merge, Direct-Read and Snoop-Ahead, achieve the
purpose of zero wait for PCI burst transfer. The post-write and
prefetch buffers are both 16 Double-Word deep FIFOs.
3.8 Snooping Control [omitted see datasheet]
3.9 AHOLD/BOFF# Process and Arbiter Interface [omitted see datasheet]
3.10 Target Initiated Termination [omitted see datasheet]
3.11 DATA Flow [omitted see datasheet]
3.12 PCI Master Read/Write DRAM Cycle [omitted see datasheet]
***Configurations:...
***Features:...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro
***Notes (Unverified Information!):...
***5600 c:Nov98...
***600 ?...
***620 c:Apr99...
***621 ?...
***630/630E/S c:Feb00...
***630ST/ET ?...
***633/633T c:Mar01...
***635/635T c:Mar01...
***640T c:Mar01 ...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95
***Info:...
***Configurations:...
***Features:
o PCI/ISA Green PC Ready
o High Integration
- VT82C575M system controller
- VT82C576M PCI bus controller
- Two instances of the VT82C577M data buffers
- Glueless interface to the VT82C416 integrated clock generator,
real time clock with extended CMOS, plug and play control and
keyboard controller with PS/2 mouse support
- Ten TTLs for a complete main board implementation
o Flexible CPU Interface
- 64-bit P54C, Pentium, K5 and M1 CPU interface
- 3.3v or 5v CPU and cache interface
- CPU external bus speed up to 66Mhz (internal 150Mhz and above)
- Supports CPU internal write-back cache
- Concurrent CPU/cache and PCI/DRAM operation
- System management interrupt, memory remap and STPCLK mechanism
- Cyrix M1 linear burst support
- CPU NA#/Address pipeline capability
o Advanced Cache Controller
- Direct map write back or write through secondary cache
- Burst Synchronous (Pipelined or non-pipelined), asynchronous
SRAM and Cache Module support
- Eight-pin CWE# and GWE# control options
- Flexible cache size: 0K/128K/256K/512K/1M/2MB
- 32 byte line size to match the primary cache
- Integrated 10-bit tag comparator
- Interleaved SRAM access
- 3-1-1-1 read/write timing for Burst Synchronous SRAM access
at 66Mhz
- 3-2-2-2 (read) and 4-2-2-2 (write) timing for interleaved
asynchronous SRAM access at 66Mhz
- Data streaming for simultaneous primary and secondary cache
line fill
- System and video BIOS cacheable and write-protect
- Programmable cacheable region and cache timing
- Optional combined tag and alter bit SRAM for write-back scheme
o Fast DRAM Controller
- Concurrent DRAM Writeback
- Four levels of CPU/cache to DRAM write buffer
- Standard Page Mode/EDO/Burst EDO-DRAM support in a flexible/
mixed combination
- EDO-DRAM auto-detect
- Mixed 256K/512K/1M/2M/4M/8M/16MxN DRAMs
- 8 banks up to 512MB DRAMs
- Flexible row and column addresses
- 64 bit or 32 bit data width
- Burst read and write operation
- Programmable DRAM timing
- BIOS shadow at 16KB increment
- System management memory remapping
- Decoupled and burst DRAM refresh with staggered RAS timing
- CAS-before-RAS refresh timing
o Intelligent PCI Bus Controller
- 32 bit PCI interface
- PCI Master snoop ahead and snoop filtering
- Concurrent PCI master/CPU/IDE operations
- Synchronous Bus to CPU clock with divide-by-two from the CPU
clock
- Multiple accelerated schemes for high bus throughput
- Automatic detection of data streaming burst cycles from CPU to
the PCI bus
- Four level of CPU to PCI posted write buffers
- Byte merging in the write buffers to reduce the number of PCI
cycles and to create further PCI bursting possibilities
- PCI to system memory data streaming up to 110Mbyte/sec
- Four level of post write buffers from PCI masters to DRAM
- Four level of prefetch buffers from DRAM for access by PCI
masters
- Zero wait state PCI master and slave burst transfer rate
- Complete steerable PCI interrupts
- IDE and ISA bus through peer PCI bus to avoid slower traffic
blocking the regular PCI bus
- PCI-2.1 compliant
o Enhanced Master Mode PCI IDE Controller
- Dual channel master mode PCI supports four Enhanced IDE devices
- Mode 4 and Mode 5 transfer rate up to 22MB/sec
- Sixteen doubleword of prefetch and write buffers
- Interlaced commands between two channels
- Separate IDE data bus and control signals from the PCI and ISA
bus to reduce loading and to enhance performance
- Bus master programming interface for ATA controllers SFF-8038
rev.1.0 compliant
- Full scatter and gather capability
- Support ATAPI compliant devices
- Support PCI native and ATA compatibility modes
- Complete software driver support
o Plug and Play Controller
- Dual interrupt and DMA signal steering with plug and play control
- Two programmable chip selects
- Microsoft Windows 95TM and plug and play BIOS compliant
o Sophisticated Power Management Unit
- Normal, doze, sleep, suspend and conserve modes
- System event monitoring with two event classes
- One idle timer, one peripheral timer and one general purpose
timer
- More than ten general purpose Input/Output ports
- Six external event input ports with programmable SMI condition
- Complete leakage control when external component is in power off
state
- Primary and secondary interrupt differentiation for individual
channels
- Clock stretching, clock throttling and clock stop control
- Multiple internal and external SMI sources for flexible power
management models
- APM 1.1 compliant
o Synchronous ISA Bus Controller
- Synchronous ISA bus clock
- Programmable wait state, command delay and IO recovery time
- Bus conversion and data alignment
- Hardware and software de-turbo control
- Fast reset and Gate A20 operation
- Integrated 82C206 peripheral controller
- Edge trigger or level sensitive interrupt
- Flash EPROM and combined BIOS support
o Built-in nand-tree pin scan test capability
o 0.6um mixed voltage, high speed and low power CMOS process
o 208 pin PQFP for VT82C575M
o 208 pin PQFP for VT82C576M
o 100 pin PQFP for VT82C577M
o 100 pin PQFP for VT82C416
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
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*ZyMOS...
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