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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96
***Info:...
***Configurations:...
***Features:
o Supports Intel Pentium CPU and other compatible CPU at
75/66/60/50MHz (external clock speed)
o Supports the Pipelined Address Mode of Pentium CPU
o Supports the Full 64-bit Pentium Processor data Bus
o Supports 32-bit PCI Interface
o Integrated Second Level (L2) Cache Controller
- Write Through and Write Back Cache Modes
- 8 bits or 7 bits Tag with Direct Mapped Cache Organization
- Integrated 16K bits Dirty Ram
- Supports Pipelined Burst SRAM
- Supports 256 KBytes to 512 MBytes Cache Sizes
- Cache Read/Write Cycle of 3-1-1-1-1-1-1-1 at 66 MHz
o Integrated DRAM Controller
- Supports 3 Banks of FP/EDO SIMMs, or 2 Banks of SDRAM DIMMs
- Supports 2Mbytes to 384Mbytes of main memory
- Supports 256K/512K/1M/2M/4M/16M x N FP/EDO/SDRAM DRAM
- Supports 3V or 5V DRAM.
- Supports Symmetrical and Asymmetrical DRAM.
- Supports 32 bits/64 bits mixed mode configuration
- Supports Concurrent Write Back for FP/EDO DRAM
- Supports Mixed DRAM (FP/EDO/SDRAM) Technology
- Supports CAS before RAS Refresh
- Supports Relocation of System Management Memory
- Programmable CAS# ,RAS#, RAMW# and MA Driving Current
- Fully Configurable for the Characteristic of Shadow RAM (640
KBytes to 1 MBytes)
- Supports FP DRAM 5-3-3-3(-3-3-3-3) Burst Read Cycles
- Supports EDO DRAM 4/5-2-2-2(-2-2-2-2) Burst Read Cycles
- Supports SDRAM 6/7-1-1-1(-2-1-1-1) Burst Read Cycles
- Supports X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
- Supports 8 Qword Deep Buffer for Read/Write Reordering, Dword
Merging and 3/2-1-1-1 Post write Cycles
- Two Programmable Non-Cacheable Regions
- Option to Disable Local Memory in Non-Cacheable Regions
- Shadow RAM in Increments of 16 KBytes
o Integrated PMU Controller
- Supports SMM Mode of CPU
- Supports CPU Stop Clock
- Supports Break Switch
- Supports Modem Ring Wakeup
- Supports Automatic Power Supply Control
o Provides High Performance PCI Arbiter.
- Supports 3 internal masters and 5 external PCI Masters
- Supports Rotating Priority Mechanism
- Hidden Arbitration Scheme Minimizes Arbitration Overhead.
- Supports Concurrency between CPU to Memory and PCI to PCI.
o Integrated Host-to-PCI Bridge
- Supports Asynchronous/Synchronous PCI Clock
- Translates the CPU Cycles into the PCI Bus Cycles
- Provides CPU-to-PCI Read Assembly and Write Disassembly
Mechanism
- Translates Sequential CPU-to-PCI Memory Write Cycles into PCI
Burst Cycles
- Zero Wait State Burst Cycles
- Supports 8 DW Deep Buffer for CPU-to-PCI Posted Write Cycles
- Supports Pipelined Process in CPU-to-PCI Access
- Supports Advance Snooping for PCI Master Bursting
- Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
- Fast back-to-back
o Integrated Posted Write Buffers and Read Prefetch Buffers to
Increase System Performance
- CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep, Always
Sustains 0 Wait Performance on CPU-to-Memory.
- CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
- PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep, Always
Streams 0 Wait Performance on PCI-to/from-Memory Access
- PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
o Built-in one 32-bit General Purpose Register
o Integrated PCI-to-ISA Bridge
- Translates PCI Bus Cycles into ISA Bus Cycles
- Translates ISA Master or DMA Cycles into PCI Bus Cycles
- Provides a Dword Post Buffer for PCI to ISA Memory cycles
- Two 32 bit Prefetch/Post Buffers Enhance the DMA and ISA Master
Performance
- Fully Compliant to PCI 2.1
o Enhanced DMA Functions
- 8-, 16- bit DMA Data Transfer
- ISA compatible, and Fast Type F DMA Cycles
- Two 8237A Compatible DMA Controllers with Seven Independent
Programmable Channels
- Provides the Readability of the two 8237 Associated Registers
o Built-in Two 8259A Interrupt Controllers
- 14 Independently Programmable Channels for Level- or Edge-
triggered Interrupts
- Provides the Readability of the two 8259A Associated Registers
o Three Programmable 16-bit Counters compatible with 8254
- System Timer Interrupt
- Generates Refresh Request
- Speaker Tone Output
- Provides the Readability of the 8254 Associated Registers
o Built-in Keyboard Controller
- Hardwired Logic Provides Instant Response
- Supports PS/2 Mouse
- Support Hot Key "Sleep" Function
o Built-in Real Time Clock(RTC) with 256B CMOS SRAM
o Fast PCI IDE Master/Slave Controller
- Fully Compatible with PCI Local Bus Specification V2.1
- Supports PCI Bus Mastering
- Plug and Play Compatible
- Supports Scatter and Gather
- Supports Dual Mode Operation - Native Mode and
Compatibility Mode
- Supports IDE PIO Timing Mode 0, 1, 2 of ANSI ATA Specification
- Supports Mode 3 and Mode 4 Timing Proposal on Enhanced IDE
Specification
- Supports Multiword DMA Mode 0, 1, 2
- Separate IDE Bus
- Two 8x32-bit FIFO for PCI Burst Read/Write Transfers.
o Universal Serial Bus Controller
- Host/Hub Controller
- Two USB ports
o On-Board Plug and Play Support
- One Steerable DMA Channel
- One Steerable Interrupt
- One Programmable Chip Select
o Supports the Reroutibility of the four PCI Interrupts
o Supports Flash ROM
o 480-Pin BGA Package
o 0.5 μm CMOS Technology
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
**UM82C*** (IBM/INTEL Direct replacement) c87
Note: Dates vary for when these chips were first available. Two
databooks have been used one from '86 the other from '91. Not all the
chips are listed in the '86 databook, the date of '87 is an
assumption.
PC/XT:
IBM: UMC: Desc:
Intel 8284 UM82C84A 25MHz CMOS Clock Generator and Driver
Intel 8288 UM82C88 Bus Controller
Intel 8259 UM8259A Programmable Interrupt Controller also UM82C59A-2 (CMOS version)
Intel 8237 UM8237A 3-5MHz Programmable DMA Controller (DMAC)
Intel 8253 UM8253*2 2.6-5MHz Programmable Interval Timer
Intel 8255 UM82C55A* Programmable Peripheral Interface
Note: * indicates: possible compatibility, datasheet does not state
explicitly. YMMV.
Note: *2 indicates: The UM8253 can be replaced with the
UM82C54/-2. The datasheet says it is a superset of the 8253, and
works up to 10MHz. Also it's compatible with the 8254. AT: IBM:
UMC: Desc: Intel 82284 UM82C284* 10-12.5MHz Clock Generator and
Ready Interface Intel 82288 UM82C288* 10-12.5MHz Bus Controller
Intel 8254 UM82C54/-2 8-10MHz CMOS Programmable Interval Timer
Intel 8259 UM8259A Programmable Interrupt Controller also
UM82C59A-2 (CMOS version) Intel 8237 UM8237A 3-5MHz Programmable
DMA Controller (DMAC) 74LS612 UM74HCT612* Memory Mapper MC146818
RTC UM82C6818* Real-Time Clock (RTC) Intel 8047 ?? Keyboard
Controller
Note: * indicates: possible compatibility, datasheet does not state
explicitly. YMMV.
**UM82C088 PC/XT Integration Chip <91...
**UM82C230 286AT MORTAR Chip Set <91
***Info:
The UMC's MORTAR (286AT) Chip Set UM82C230 series provides an economic
alternative for building a reliable IBM PC/AT compatible system. A
commercial 12MHZ/0 wait state, 4MByte main memory system and
math-coprocessor can be easily built by using 3 VLSIs, 8 logic
components plus memory and processor.
The UM82C230 MORTAR chipset consists of the UM82C231 System/Memory
Controller, the UM82C232 Data/Address Buffer and the UM82C206
Integrated Peripherals Controller (IPC).
As shown in the System Block Diagram, [see datasheet] there are three
data buses: local data bus, AT data bus and peripheral data (XD) bus.
The local DRAM, EPROM and Numerical Processor are located on the local
data bus. The UM82C206 and 8042 Keyboard Controller sit on the XD bus.
The AT data bus was driven by the UM82C232 directly which conveys the
data to/from the AT Channel Adaptors.
The address bus architecture is also very simple; local CPU address
bus, local DRAM address bus (MA), peripheral address bus (XA) and AT
address bus. The local address bus is shared between CPU, UM82C231 and
UM82C206. The MA bus is used by the local DRAM only. Most of the
system board devices are attached to the XA bus, like UM82C232,
UM82C206, ROMs and 8042. Some AT address lines are driven by the
UM82C231 or UM82C232 directly; the others are buffered.
The UM82C231 provides synchronization and control signals for all
buses. The UM82C231 also distinguishes if the current cycle is local
memory cycle. Upon detecting that it is a local DRAM cycle, no AT
control signals are sent out to the AT channel. The UM82C231 is based
on the memory configurations to complete the current cycle with
fastest response. If the cycle is AT cycle, the UM82C231 sends out the
control signals sequentially which are then used by the adaptors or
system board devices to receive the write data or to send the fetched
data. Then, depending on the status signals sent back by the adaptors
or system board devices, the UM82C231 determines which kind of AT
cycles to perform: 8-bit, 16-bit, bus conversion, wait state insert,
or wait state cycle.
The UM82C232 Data/Address buffer provides the buffering and latching
between the CPU local data bus, AT bus and XD bus. The parity bit
generation and parity bit checking logic resides in the UM82C232 also.
During DMA cycles, the UM82C232 latches the address from XD, which is
sent by the UM82C206, and transfers to XA bus.
***Configurations:...
***Features:...
**UM82C210 386SX/286 AT Chip Set <91...
**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?...
**UM82C380 386 HEAT PC/AT Chip Set <91...
**UM82C480 386/486 PC Chip Set c91...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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