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**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION
The 82489DX Advanced Programmable Interrupt Controller provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.
The main function of the 82489DX is to provide interrupt management
across all processors. This dynamic interrupt distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in systems with multiple I/O subsystems, where each subsystem
can have its own set of interrupts. This chip also provides
inter-processor interrupts, allowing any processor to interrupt any
processor or set of processor. Each 82489DX I/O init interrupt input
pin is individually programmable by software as either edge or level
triggered. The interrupt vector and interrupt steering information an
be specified per pin. A 32-bit wide timer is provided that can be
programmed to interrupt the local processor. the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate time slice interrupts locally to that processor. the
82489DX provides 32-bit software access to its internal
registers. Since no 82489DX register read have any side effects, the
82489DX registers can be aliased to a user read-only page for fast
user access (e.g., performance monitoring timers).
The 82489DX supports a generalized naming/addressing scheme that can
be tailored by software to fit a variety of system architectures and
usage models. It also supports 8259A compatibility by becoming
virtually transparent with regard to an externally connected 8259A
style controller, making the 8259A visible to software.
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96
***Notes:...
***Info:
The OPTi Viper-N+ chipset is the leading solution for PCI-based mobile
applications. Viper-N+ features leading edge power management
capability and flexibility for Intel Pentium 75/90/100/120 and Cyrix
6x86 processor based notebooks. The chipset incorporates desktop-like
performance features such as L1 and L2 cache support, a full 64-bit
DRAM controller and an integrated PCI controller, in a highly
integrated three chip set.
In terms of advanced power management, no chipset offers a more
effective, comprehensive or flexible feature set, allowing for maximum
performance with minimum power consumption for extended battery
life. In fact, for typical applications, Viper-N+'s power management
unit reduces power consumption by as much as 80%.
Viper-N+ offers the highest level of system integration, enabling the
lowest system cost and real estate requirement for Pentium-PCI
notebooks. A system without TTL is achievable with synchronous cache.
And, PCI offers easy upgradability to emerging standard interfaces,
such as PCMCIA/CardBus and PCI docking stations. Viper-N+ also
features an integrated local bus IDE controller to avoid ISA data bus
bottlenecks.
OPTi coupled its expertise in mobile technology and PCI-based design
to create its second generation 64-bit CPU mobile chipset. The result
is Viper-N+, enabling the highest levels of performance, system
integration and power management capability available for Pentium
PCI-based mobile systems.
***Configurations:...
***Features:...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**950 LPC I/O <07/16/99
***Info:...
***Versions:...
***Features:
o Low Pin Count Interface
- Comply with Intel LPC Interface Specification Rev. 1.0
(Sept. 29, 1997)
- Supports Serial IRQ Protocol
- Supports PCI PME# Interface
o PC98/PC99, ACPI Compliant
- PC98 & PC99 compliant
- Register sets compatible with "Plug and Play ISA Specification
Rev. 1.0a"
- ACPI V. 1.0 compliant
- Supports 9 logical devices
o Enhanced Hardware Monitor
- Built-in 8-bit Analog to Digital Converter
- 3 thermal inputs from remote thermistors or thermal diode or
diode-connected transistor
- 8 voltage monitor inputs (VBAT is measured internally.)
- WatchDog comparison of all monitored values
o Fan Speed Controller
- Provides Fan ON/OFF and PWM control
- 3 programmable Pulse Width Modulation (PWM) Fan control outputs
- Each PWM output supports 128 steps of PWM modes
- Monitors 3 Fan tachometer inputs
o Game Port
- Built-in 558 quad timers and buffer chips
- Supports direct connection of two joysticks
- Game port signals are multiplexed with GPIOs
o Two 16C550 UARTs
- Supports two standard Serial ports
- UART1 is dedicated for Serial port
- UART2 supports either Serial Port or IrDA 1.0/ASKIR
o Consumer Remote Control (TV remote) IR with Power-up Feature
o IEEE 1284 Parallel Port
- Standard mode -- Bi-directional SPP compliant
- Enhanced mode -- EPP V. 1.7 and 1.9 compliant
- High speed mode -- ECP, IEEE 1284 compliant
- Backdrive current reduction
- Printer power-on damage reduction
− Supports POST (Power-On Self Test) Data Port
o Floppy Disk Controller
- Supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M floppy
disk drives
- Enhanced digital data separator
- 3-Mode drives supported
- Supports automatic write protection via software
o 48 General Purpose I/O Pins
- Input mode supports switch de-bounce
- SMI is routed through GPIOs
o Flash ROM Interface
- Up to 4M bits flash supported
o Single 24/48 MHz Clock Inputs
o Single +5V Power Supply
o 128-Pin PQFP
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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