[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96
***Info:
[no general section in datasheet]
3. Functional Description
3.1 DRAM Controller
3.1.1 DRAM Type
The SiS5571 can support up to 384MBytes (3 banks) of DRAMs and each
bank could be single or double sided 64 bits FP (Fast Page mode) DRAM,
EDO (Extended Data Output) DRAM, and SDRAM (Synchronous DRAM)
DRAM. Half populated bank(32-bit) is also supported.
The installed DRAM type can be 256K, 512k, 1M, 2M, 4M or 16M bit deep
by n bit wide DRAMs, and both symmetrical and asymmetrical type DRAM
are supported. It is also permissible to mix the DRAMs (FP/EDO/SDRAM)
bank by bank and the corresponding DRAM timing will be switched
automatically according to register settings.
3.1.2 DRAM Configuration
The SiS5571 can support single sided or double sided DRAM modules for
each bank. The basic configurations are shown as the following:
3.1.3 Double-sided DRAM [omitted see datasheet]
3.1.4 Single-sided DRAM [omitted see datasheet]
3.1.5 DRAM Scramble Table [omitted see datasheet]
3.1.6 64-bit mapping table [omitted see datasheet]
3.2 DRAM Performance [omitted see datasheet]
3.3 CPU to DRAM Posted Write FIFOs
There is a built-in CPU to Memory posted write buffer with 8 QWord
deep ( CTMFF). All the write access to DRAM will be buffered. For the
CPU read miss / Line fill cycles, the write- back data from the second
level cache will be buffered first, and right after the data had been
posted write into the FIFO, CPU can performs the read operation by the
memory controller starting to read data from DRAMs. The buffered data
are then written to DRAM whenever no any other read DRAM request
comes. With this concurrent write back policy, many wait states are
eliminated. If there comes a bunch of continuous DRAM write cycles,
some ones will be pending if the CTMFF is full.
3.4 32-bit (Half-Populated) DRAM Access
For the read access, there will be either single or burst read cycle
to access the DRAM which depends on the cacheability of the cycle. If
the current DRAM configuration is half-populated bank, then the
SiS5571 will assert 8 consecutive cycles to access DRAM for the burst
cycle. For the single cycle that only accesses DRAM within a DWord,
the SiS5571 will only issue one cycle to access DRAM. For the single
cycle that accesses one Qword or cross DWord boundary, the SiS5571
will issue two consecutive cycles to access DRAM.
3.5 Arbiter
The arbiter is the interface between the DRAM controller and the host
which can access DRAMs. In addition to pass or translate the
information from outside to DRAM controller, arbiter is also
responsible for which master has higher priority to access DRAMs. The
arbiter treats different DRAM access request as DRAM master, and that
makes there be 5 masters which are trying to access DRAMs by sending
their request to the arbiter. After one of them get the grant from the
arbiter, it owns DRAM bus and begins to do memory data transaction.
The masters are: CPU read request, PCI master, Posted write FIFO write
request, and Refresh request. The order of these masters shown above
also stands for their priority to access memory.
3.6 Refresh cycle
The refresh cycle will occur every 15.6 us. It is timed by a counter
of 14Mhz input. The CAS[7:0]# will be asserted at the same time, and
the RAS[5:0]# are asserted sequentially.
3.7 PCI bridge
SiS5571 is able to operate at both asynchronous and synchronous PCI
clocks. Synchronous mode is provided for those synchronous system to
improve the overall system performance. While in the PCI master write
cycles, post-write is always performed. And function of Write Merge
with CPU-to-DRAM post-write buffer is incorporated to eliminate the
penalty of snooping write-back. On the other hand, prefetch is enabled
for master read cycles by default, and such function could be disabled
optionally. And, Direct-Read from CPU-to-DRAM post-write buffer is
implemented to eliminate the overhead of snooping write-back also. In
addition to Write-Merge and Direct-Read, Snoop-Ahead also hides the
overhead of inquiry cycles for master to main memory cycles. These key
functions, Write-Merge, Direct-Read and Snoop-Ahead, achieve the
purpose of zero wait for PCI burst transfer. The post-write and
prefetch buffers are both 16 Double-Word deep FIFOs.
3.8 Snooping Control [omitted see datasheet]
3.9 AHOLD/BOFF# Process and Arbiter Interface [omitted see datasheet]
3.10 Target Initiated Termination [omitted see datasheet]
3.11 DATA Flow [omitted see datasheet]
3.12 PCI Master Read/Write DRAM Cycle [omitted see datasheet]
***Configurations:...
***Features:...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98
***Info:
The P5 A.G.P./VGA chipset, SiS530/5595, provides a high performance/
cost index Desktop/Mobile solution for the Intel Pentium P54C/P55C,
AMD K5/K6/K6-II, Cyrix M1/M2 and other compatible Pentium CPU with 3D
A.G.P. VGA system.
The Host, PCI, 3D A.G.P. Video/Graphics & Memory Controller, SiS530
integrates the Host- to-PCI bridge, the PCI interface, the L2 cache
controller, the DRAM controller, the high performance hardware 2D/3D
VGA controller, and the PCI IDE controller.
The Host interface supports Synchronous/Asynchronous Host/DRAM
clocking configuration to eminently improve the system performance and
DRAM compatibility issues.
The L2 cache controller can support up to 2 MB P.B. SRAM, and the DRAM
controller can support SDRAM memory up to 1.5 GBytes with three
double-sided SDRAM DIMMs configuration. The cacheable DRAM sizes
support up to 256 MBytes.
The built-in fast PCI IDE controller supports the ATA PIO/DMA, and the
Ultra DMA33/66 function that support the data transfer rate up to 66
MB/s. It provides the separate data path for two IDE channels that can
eminently improve the performance under the multi-tasking environment.
The A.G.P. internal interface is supported for integrated H/W 3D VGA
controller. The integrated VGA controller is a high performance and
targeted at 3D graphics application. In addition, the integrated 3D
Video/Graphics controller adopts the 64bits 100MHz host bus interface
high technology to improve the performance eminently. To cost-
effective the PC system, the share system memory architecture will be
adopted and it can flexibly using the 2MB, 4MB and 8MB frame buffer
size from programming the system BIOS. [something got confused in
translation there didn't it?] To enhance the system performance,
SiS530 also supports the local frame buffer solution and memory sizes
can support up to 8MB with SDRAM and SGRAM.
In addition to provide the standard interface for CRT monitors, it
also provides the Digital Flat Panel Port (DFP) for a standard
interface between a personal computer and a digital flat panel
monitor. This port allows a host computer to connect directly to an
external flat panel monitor without the need for analog-to-digital
conversion found in most flat panel monitors today. As for DVD
solution, the integrated 3D VGA controller also support DVD H/W
accelerator to improve the DVD playback performance.
The SiS5595 PCI system I/O integrates the PCI-to-ISA bridge with the
DDMA, PC/PCI DMA and Serial IRQ capability, the ACPI/Legacy PMU, the
Data Acquisition Interface, the Universal Serial Bus host/hub
interface, and the ISA bus interface which contains the ISA bus
controller, the DMA controllers, the interrupt controllers, the Timers
and the Real Time Clock (RTC). It also integrates the Keyboard
Controller and PS/2 mouse interface that can support keyboard power on
function for users to power on system by entering the hot key or
password from keyboard. The built-in USB controller, which is fully
compliant to OHCI (Open Host Controller Interface), provides two USB
ports capable of running full/low speed USB devices. The Data
Acquisition Interface offers the ability of monitoring and reporting
the environmental condition of the PC. It could monitor 5 positive
analog voltage inputs, 2 Fan speed inputs, and one temperature input.
In addition, SiS5595 also supports ACPI function to meet Advanced
Configuration and Power Interface (ACPI) 1.0 specification for Windows
98 environment, it can support power-management timer, Power button,
Real-time clock alarm wake up, more sleeping state, ACPI LED for
sleeping and working state, LAN wake up, Modem Ring In wake up, and
OnNow initiative function.
***Configurations:...
***Features:...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved