[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset                <01/09/95
***Notes:...
***Info:...
***Configurations:...
***Features:...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset                <04/02/95...
**5120           Pentium PCI/ISA Chipset (Mobile)            <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset                <04/02/95...
**5511/5512/5513 Pentium PCI/ISA                             <06/14/95...
**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96...
**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96
***Info:...
***Configurations:...
***Features:...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98
***Info:...
***Configurations:...
***Features:
o   Supports Intel/AMD/Cyrix/IDT Pentium CPU Host Bus at 
    66/75/83/95/100 MHz and 2.5/3.3V Bus Interface
    − Supports the Pipelined Address of Pentium compatible CPU
    − Supports the Linear Address Mode of Cyrix CPU
    − 100/100, 95/95, 83/83, 75/75 and 66/66 MHz Synchronous 
      Host/DRAM clocking configuration
    − 100/75, 95/75, 83/66, 66/100 and 66/83 MHz Asynchronous 
      Host/DRAM clocking configuration
    − Supports Host Bus operation for integrated 3D VGA Controller
o   Meets PC99 Requirements
o   Supports PCI Revision 2.2 Specification
o   Integrated Super AGP VGA for Hardware 2D/3D Video/Graphics 
    Accelerators
    − Supports tightly coupled 64 bits 100MHz host interface to VGA 
      to speed up GUI performance and the video playback frame rate
    − Built-in programmable 24-bit true-color RAMDAC up to 230 MHz 
      pixel clock
    − Built-in reference voltage generator and monitor sense circuit
    − Supports loadable RAMDAC for gamma correction in high color 
      and true color modes
    − Built-in dual-clock generator
    − Supports Multiple Adapters and Multiple Monitors
    − Built-in PCI multimedia interface
    − Flexible design for shared frame buffer or local frame buffer 
      architecture
    − Shared System Memory Area 2MB, 4MB and 8MB
    − Supports SDRAM and SGRAM local frame buffer and memory size up 
      to 8 MB
    − Supports Digital Flat Panel Port for Digital Monitor (LCD Panel)
    − Supports DVD H/W Accelerator
o   Integrated Second Level ( L2 ) Cache Controller
    − Write Back Cache Mode
    − Direct Mapped Cache Organization
    − Supports Pipelined Burst SRAM
    − Supports 256K/512K/1M/2M Bytes Cache Sizes
    − Cache Hit Read/Write Cycle of 3-1-1-1
    − Cache Back-to-Back Read Cycle of 3-1-1-1-1-1-1-1
    − Supports Single Read Allocation for L2 Cache
    − Supports Concurrency of CPU to L2 cache and Integrated A.G.P. 
      VGA master to DRAM accesses
o   Integrated DRAM Controller
    − Supports up to 3 double sided DIMMs (6 rows memory)
    − Supports 8Mbytes to 1.5 GBytes of main memory
    − Supports Cacheable DRAM Sizes up to 256 MBytes
    − Supports 1M/2M/4M/8M/16M/32M x N for 2-bank or 4-bank SDRAM
    − Supports 3.3V DRAM
    − Supports Concurrent Write Back
    − Supports CAS before RAS Refresh, Self Refresh
    − Supports Relocation of System Management Memory
    − Programmable CS#, DQM#, SRAS#, SCAS#, RAMWE# and MA Driving 
      Current
    − Option to Disable Local Memory in Non-cacheable Regions
    − Entries GART cache to Minimize the Number of Memory Bus Cycles 
      Required for Accessing Graphical Texture Memory
    − Programmable Counters to Ensure Guaranteed Minimum Access Time 
      for Integrated A.G.P. VGA, CPU, and PCI accesses
    − Two Programmable Non-cacheable Regions
    − Supports X-1-1-1/X-2-2-2 Burst Write Cycles
    − Fully Configurable for the Characteristic of Shadow RAM (640 
      KBytes to 1 MBytes)
    − Shadow RAM in Increments of 16 KBytes Built-in 8 Way 
      Associative/16
    − Supports SDRAM 7/8-1-1-1 Burst Read Cycles
o   Provides High Performance PCI Arbiter
    − Supports up to 4 PCI Masters
    − Supports Rotating Priority Mechanism
    - Hidden Arbitration Scheme Minimizes Arbitration Overhead
    - Supports Concurrency between CPU to Memory and PCI to PCI
    - Supports Concurrency between CPU to 33Mhz PCI Access and 33Mhz 
      PCI to integrated A.G.P. VGA Access
    - Programmable Timers Ensure Guaranteed Minimum Access Time for 
      PCI Bus Masters, and CPU
o   PCI Bus Interface
    - Supports 32-bit PCI local bus standard Revision 2.2 compliant
    - Integrated write-once subsystem vendor ID configuration register
    - Supports zero wait-state memory mapped I/O burst write
    - Integrated 2 stages PCI post-write buffer to enhance frame 
      buffer write performance
    - Integrated 256 bits read cache to enhance frame buffer read 
      performance
    - Supports full 16-bit re-locatable VGA I/O address decoding
o   Integrated Host-to-PCI Bridge
    - Supports Asynchronous PCI Clock
    - Translates the CPU Cycles into the PCI Bus Cycles
    - Zero Wait State Burst Cycles
    - Supports Pipelined Process in CPU-to-PCI Access
    - Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
    - Supports Memory Remapping Function for PCI master accessing 
      Graphical Window
o   Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
    - Supports Graphic Window Size from 4MBytes to 256MBytes
    - Supports Pipelined Process in CPU-to-Integrated 3D A.G.P. 
      VGA Access
    - Supports 8 Way, 16 Entries Page Table Cache for GART to enhance 
      Integrated A.G.P. VGA Controller Read/Write Performance
    - Supports PCI-to-PCI bridge function for memory write from 33Mhz 
      PCI bus to Integrated A.G.P. VGA
o   Integrated Posted Write Buffers and Read Prefetch Buffers to 
    Increase System Performance
    - CPU-to-Memory Posted Write Buffer (CTMFF) with 12QW Deep, Always 
      Sustains 0 Wait Performance on CPU-to-Memory
    - CPU-to-Memory Read Buffer with 4 QW Deep
    - CPU-to-PCI Posted Write Buffer with 2 QW Deep
    - PCI-to-Memory Posted Write Buffer with 8 QW Deep, Always 
      Streams 0 Wait Performance on PCI-to/from-Memory Access
    - PCI-to-Memory Read Prefetch Buffer with 8 QW Deep
    - CPU-to-VGA Posted Write Buffer with 4 QW Deep
o   Fast PCI IDE Master/Slave Controller
    - Bus Master Programming Interface for Windows 98 Compliant 
      Controller
    - Plug and Play Compatible
    - Supports Scatter and Gather
    - Supports Dual Mode Operation - Native Mode and Compatibility 
      Mode
    - Supports IDE PIO Timing Mode 0, 1, 2 ,3 and 4
    - Supports Multiword DMA Mode 0, 1, 2
    - Supports Ultra DMA 33/66
    - Two Separate IDE Bus
    - Two 16 DW FIFO for PCI Burst Transfers.
o   Supports NAND Tree for Ball Connectivity Testing
o   576-Balls BGA Package
o   3.3V Core with mixed 2.5V, 3.3V and 5V I/O CMOS Technology

**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**????????         Cheetah 486, PCI [no datasheet]                   ?
***Info:...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

(c) Copyright mR_Slugs Warehouse - All rights Reserved