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**M1217/M1209    386SX/SLC Single Chip (40MHz)    [no datasheet]   c91
***Notes:...
**M1219          386DX/486 ISA Cache? Single Chip [no datasheet]     ?
**M1419          386DX/486 ISA Cache  Single Chip [no datasheet]   c91
**Ml429/31/35    486 VLB/PCI/ISA      [no datasheet, some info] cOct93...
**M1439/31/45    486 VLB/PCI/ISA      [no datasheet, some info] <May95...
**M1489/87       FinALi-486 PCI Chipset                         <Feb95...
**M????          Genie, Quad Pentium  [no datasheet, some info]    c95...
**M1451/49       Aladdin    (Pentium) [no datasheet]                 ?...
**M1511/12/13    Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23       Aladdin III       50-66MHz                     <Nov96...
**M1531/33/43    Aladdin IV & IV+  50-83.3MHz                <05/28/97...
**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset                <01/09/95
***Notes:...
***Info:...
***Configurations:...
***Features:...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset                <04/02/95...
**5120           Pentium PCI/ISA Chipset (Mobile)            <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset                <04/02/95...
**5511/5512/5513 Pentium PCI/ISA                             <06/14/95...
**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96...
**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98
***Info:...
***Configurations:...
***Features:
o   Support Intel/AMD/Cyrix Pentium CPU and Other Compatible CPU 
    Host Bus at 60/66 MHz and 3.3V Bus Interface
    − Support the Pipelined Address of Pentium compatible CPU
    − Support the Linear Address Mode of Cyrix CPU
o   Support the Pipelined Address Mode of Pentium CPU
o   Fully Compliant to A.G.P. Revision 1.0 Specification
o   Meet PC97 Requirements
o   Supports PCI Revision 2.1 Specification
o   Integrated Second Level (L2) Cache Controller
    - Write Back Cache Mode
    - Support L2 Cache Flushing for entire L2 cache or specific 
      4K page
    - 8 bits or 7 bits Tag with Direct Mapped Cache Organization
    - Integrated 32K bits Dirty SRAM
    - Integrated 32K bits Invalid SRAM
    - Support Pipelined Burst SRAM
    - Support 256K/512K/1MBytes Cache Sizes
    - Cache Hit Read/Write Cycle of 3-1-1-1
    - Cache Back-to-Back Read/Write Cycle of 3-1-1-1-1-1-1-1
    - Support Single Read Allocation for L2 Cache
    - Support Concurrency of CPU to L2 cache and A.G.P. master to 
      DRAM accesses
o   Integrated DRAM Controller
    - Support 6 RAS Lines for FPM/EDO/SDRAM DIMMs/SIMMs
    - Support 2Mbytes to 768Mbytes of main memory
    - Support Cacheable DRAM Sizes up to 256 MBytes.
    - Support 256K/512K/1M/2M/4M/8M/16Mx N FPM/EDO/SDRAM DRAM
    - Support 64 Mb DRAM Technology
    - Support Parity Checker or ECC Function
    - Support 3.3V or 5V DRAM
    - Supports Symmetrical and Asymmetrical DRAM
    - Support Concurrent Write Back
    - Support CAS before RAS Refresh, Self Refresh
    - Support Relocation of System Management Memory
    - Programmable CAS#, RAS#, RAMWE# and MA Driving Current
    - Fully Configurable for the Characteristic of Shadow RAM (640 
      KBytes to 1 MBytes)
    - Support FPM DRAM 5/6-3-3-3(-3-3-3-3) Burst Read Cycles
    - Support EDO DRAM 5/6-2-2-2(-2-2-2-2) Burst Read Cycles
    - Support SDRAM 5/6/7-1-1-1(-2/3-1-1-1) Burst Read Cycles
    - Support X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
    - Two Programmable Non-cacheable Regions
    - Option to Disable Local Memory in Non-cacheable Regions
    - Shadow RAM in Increments of 16 Kbytes
    - Pseudo Directory/Page Scheme for Mapping Graphical Texture 
      Access to Physical Memory Address
    - Built-in 8 Way Associative/16 Entries GART cache to Minimize the 
      Number of Memory Bus Cycles Required for Accessing Graphical 
      Texture Memory
    - Programmable Counters to Ensure Guaranteed Minimum Access Time 
      for A.G.P., CPU, and PCI accesses
o   Provides High Performance PCI Arbiter.
    - Support up to 5  PCI Masters
    - Support Rotating Priority Mechanism
    - Hidden Arbitration Scheme Minimizes Arbitration Overhead.
    - Support Concurrency between CPU to Memory and PCI to PCI
    - Support Concurrency between CPU to 33Mhz PCI Access and 33Mhz 
      PCI to A.G.P. Access
    - Support Concurrency between CPU to 66Mhz PCI Access and A.G.P. 
      to 33Mhz PCI Access
    - Programmable Timers Ensure Guaranteed Minimum Access Time for 
      PCI Bus Masters, and CPU
o   Integrated Host-to-PCI Bridge
    - Support Asynchronous and Synchronous PCI Clock
    - Translates the CPU Cycles into the PCI Bus Cycles
    - Zero Wait State Burst Cycles
    - Support IDE Posted Write
    - Support Pipelined Process in CPU-to-PCI Access
    - Support Advance Snooping for PCI Master Bursting
    - Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
    - Support Memory Remapping Function for PCI master accessing 
      Graphical Window
o   Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
    - Support Asynchronous and Synchronous A.G.P. Clock
    - Support 1X, and 2X Mode for A.G.P. 66/133 MHz 3.3V device
    - Support Graphic Window Size from 4Mbytes to 256Mbytes
    - Different arbitration policy for A.G.P. devices and 66Mhz PCI 
      devices.
    - Translates Sequential CPU-to-A.G.P. Memory Write Cycles into 
      A.G.P. Bus (PCI66) Burst Cycles
    - Zero Wait State Burst Cycles
    - Support Pipelined Process in CPU-to-A.G.P. Access
    - Support Advance Snooping for A.G.P. Master initiate system 
      memory access with PCI Cycles
    - Support 8 Way, 16 Entries Page Table Cache to enhance A.G.P. 
      Read/Write Performance
    - Support Both 1-Level and 2-Level GART (Graphic Address Re-
      Mapping Table)
    - Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
    - Programmable Counters to Ensure Guaranteed Minimum Access Time 
      for Low Priority Request, CPU to A.G.P./and A.G.P. Master 
      Transaction
    - Support PCI-to-PCI bridge function for memory write from 33Mhz 
      PCI bus to A.G.P. bus
o   Integrated Posted Write Buffers and Read Prefetch Buffers to 
    Increase System Performance
    - CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep, Always 
      Sustains 0 Wait Performance on CPU-to-Memory
    - CPU-to-Memory Read Buffer with 4 QW Deep
    - CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
    - PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep, Always 
      Streams 0 Wait Performance on PCI-to/from-Memory Access
    - PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
    - CPU-to-PCI66 Posted Write Buffer(CTAFF) with 8 DW Deep
    - PCI66-to-Memory Posted Write Buffer(ATHFF) with 8 QW Deep
    - A.G.P. Request Queue With the Depth of 32
    - A.G.P. High Priority Write Queue with 64 QW Deep
    - A.G.P. Low Priority Write Queue with 64 QW Deep
    - A.G.P. High Priority Read Return Queue with 64 QW Deep
    - A.G.P. Low Priority Read Return Queue with 64 QW Deep
o   Fast PCI IDE Master/Slave Controller
    - Bus Master Programming Interface for ATA Windows 95 Compliant 
      Controller
    - Plug and Play Compatible
    - Support Scatter and Gather
    - Support Dual Mode Operation - Native Mode and Compatibility 
      Mode
    - Support IDE PIO Timing Mode 0, 1, 2 ,3 and 4
    - Support Multiword DMA Mode 0, 1, 2
    - Support Ultra DMA/33
    - Two Separate IDE Bus
    - Two 16 DW FIFO for PCI Burst Transfers.
o   Support NAND Tree for Ball Connectivity Testing
o   553-Balls BGA Package
o   0.35μm 3.3V CMOS Technology

**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers          <84
***Notes:...
***Info:...
***Versions:...
***Features:...
**TACT82000   3-Chip 286 [no datasheet]                            c89...
**TACT82411   Snake  Single-Chip AT Controller                     c90...
**TACT82S411  Snake+ Single-Chip AT Controller [no datasheet]      c91...
**TACT83000   AT 'Tiger' Chip Set (386)                            c89...
**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91...
**Other:...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

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