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**Why this document is not GPL or a wiki
The document is copyright,  it is NOT GPL'ed text. While  the GPL is a
fantastic  idea, I  have chosen  not to  make this  freely copied  and
modified. The reasons are as follows:

1. GPL text tends to be  copied...EVERYWHERE. For example, if you look
   up a subject  on wikipedia, then try to get  more information, or a
   different perspective on  say about.com.  There you  find the EXACT
   SAME  TEXT.  This  is what  mirrors  are for.   It's an  unintended
   consequence,  but  it  can  lead  to  misinformation  being  spread
   everywhere. A bigger problem.

2. There seems to be fewer  and fewer informative websites. It used to
   be that  if you  searched for  something you  would find  a website
   about a particular  subject. Now you tend to  find the encyclopedia
   and often nothing else (well quickly).

In addition the majority of this text is quotes.

The wiki  concept is a good  idea, but they have  problems. Because no
one "owns" the  work they seem to  go to two extremes.   Either no one
maintains them, or there are edit wars. Also anyone can edit them.

**Definition of a chip set:...
**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL9020  Data Controller                                       <oct88
***Info:...
***Versions:...
***Features:...
**SL9025  Address Controller                                    <oct88...
**SL9090  Universal PC/AT Clock Chip                            <oct88...
**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
**Other:...
*Motorola...
*OPTi...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?
***Notes:...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Processor interface:
    - Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D 
    - AMD 486DX, DX2, DXL, DXL2, Plus
    - Cyrix DX, DX2, M7
    - CPU frequencies supported 20, 25, 33, 40 and 50MHz
o   Cache interface:
    - Direct Mapped Cache
    - Two banks interleaved or single bank non-interleaved
    - 64, 128, 256 and 512K cache sizes
    - Programmable wait states for L2 cache reads and writes
    - 2-1-1-1 read burst and zero wait state write @ 33MHz
    - No Valid bit required
    - Supports CPUs with L1 write-back support
o   DRAM interface:
    - Up to 128MB main memory support
    - Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM 
      modules
    - Read page-hit timing of 3-2-2-2 at 33MHz
    - Supports hidden, slow and CAS-before-RAS refresh
    - Four RAS lines to support four banks of DRAM
    - Programmable wait states for DRAM reads and writes
    - Enhanced DRAM configuration map
o   Power management:
    - Support for SMM (System Management Mode) for system power 
      management implementations
    - Programmable power management
    - Programmable wake-up events through hardware, software and 
      external SMI source
    - Multiple level GREEN support (NESTED_GREEN)
    - STPCLK# protocol support
    - One programmable GREEN event timer
o   ISA interface:
    - 100% IBM PC/AT ISA compatible
    - Integrates DMA, timer and interrupt controllers
    - Optional PS/2 style IRQ1 and 12 latching
o   VESA VL interface:
    - Conforms to the VESA v2.0 specification
    - Optional support for up to two VL masters
o   Miscellaneous features:
    - Full support for shadow RAM, write protection, L1/L2 
      cacheability for video, adapter and system BIOS
    - Enhanced arbitration scheme
    - Transparent 8042 emulation for fast CPU reset and GATEA20 
      generation
o   Packaging:
    - Higher integration
    - Reduced TTL count
    - Low-power, high-speed 0.8-micron CMOS technology
    - 208-pin PQFP (Plastic Quad Flat Pack)

**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91
***Notes:...
**Other:...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...