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**Quote style:
To avoid thousands of quote marks and colliding with quote marks in
the text, I have used a modified quotation style. Anything in a
section titled "Info:" or "Features:" is a quote from a datasheet
unless otherwised stated in that section. In these sections anything
inside [] is an annotation and not part of the datasheet unless
otherwise stated in that section.
Under any other section, the text is my own unless indicated with "".
Also this document does not contain the entire datasheet for each
chip, usually only the first few pages are included to give an outline
of it. Some datasheets are 100s of pages other are only 1.
**Cant find a chip?...
**Why this document is not GPL or a wiki...
**Definition of a chip set:...
**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93
***Notes:...
***Info:...
***Configurations:...
***Features:
[features found only in the 802GP are marked in [] brackets ]
o Processor interface:
- Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D
- AMD 486SX, DX2, DXL, DXL2, Plus
- Cyrix DX, DX2, M7
- CPU frequencies supported 20, 25, 33, 40 and 50MHz
o Cache interface:
- Direct mapped cache
- Two banks interleaved or single bank non-interleaved
- 64, 128, 256 and 512K cache sizes
- Programmable wait states for L2 cache reads and writes
- 2-1-1-1 read burst and zero wait state write @ 33MHz
- No Valid bit required
[- Supports external single-chip cache modules from thyroid-party ]
[ vendors for high performance at 50MHz ]
- Supports CPUs with L1 write-back support
o DRAM interface:
- Up to 128MB main memory support
- Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM
modules
- Read page hit timing of 3-2-2-2 at 33MHz
- Supports hidden, slow. and CAS-before-RAS refresh
- Four RAS lines to support four banks of DRAM
[- Eight RAS lines to support four banks of DRAM ]
- Programmable wait states for DRAM reads and writes
[- Programmable memory holes for supporting ISA memory ]
- Enhanced DRAM configuration map
[- Strong drivers on the MA lines (12/24mA) ]
[- Supports asymmetric DRAMs ]
o Power management:
- Support for SMM (System Management Mode) for system power
management implementations
- Programmable power management
[- CPU clock control ]
- Programmable wake-up events through hardware, software, and
external SMI source
- Multiple level GREEN support (NESTED_GREEN)
- STPCLK# protocol support
[- Programmable GREEN event timer ](802G only)
[- Individually programmable peripheral ](802GP only)
o ISA interface:
- 100% IBM PC/AT ISA compatible
[- Programmable edge- or level-trigger interrupts ]
- integrates DMA, timer and interrupt controllers
[- Slew rate control for output drivers ]
- Optional PS/2 style IRQ1 and IRQ12 latching
o VESA VL interface:
- Conforms to the VESA V2.0 specification
- Optional support for up to two VL masters
o Miscellaneous features: (802G only)
- Full support for shadow RAM, write protection, L1/L2
cacheability for video, adapter, and system BIOS
- Enhanced arbitration scheme
- Transparent 8042 emulation for fast CPU reset and GATEA20
generation
o [Miscellaneous features: ](802GP only)
[- Full support for flash, write protection, L1/L2 ]
[ cacheability for video, adapter, and system BIOS ]
[- Provides Micro Channel bridge support ]
[- 10-/16-nit I/O decodes ]
[- Enhanced arbitration scheme ]
o Packaging:
- Higher integration
- Reduced TTL count
- Low-power, high~speed 0.8-micron CMOS technology
- 208-pin PQFP (Plastic Quad Flat Pack)
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
**SL82C470 'Mozart' 486/386 EISA chipset c:Dec91
***Info:...
***Configurations:...
***Features:...
**SL82C490 'Wagner' 486? [no datasheet] ?...
**SL82C550 'Rossini' Pentium [no datasheet] c:95...
**
**Support Chips:
**SL82C365 Cache Controller (for 386DX/SX) c:91...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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