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**SL9020  Data Controller                                       <oct88
***Info:...
***Versions:...
***Features:...
**SL9025  Address Controller                                    <oct88...
**SL9090  Universal PC/AT Clock Chip                            <oct88...
**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
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**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?
***Notes:...
**82C802G/GP     System/Power Management Controller (cached)      c:93
***Notes:...
***Info:...
***Configurations:...
***Features:
[features found only in the 802GP are marked in [] brackets ]

o   Processor interface:
    - Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D
    - AMD 486SX, DX2, DXL, DXL2, Plus
    - Cyrix DX, DX2, M7
    - CPU frequencies supported 20, 25, 33, 40 and 50MHz
o   Cache interface:
    - Direct mapped cache
    - Two banks interleaved or single bank non-interleaved
    - 64, 128, 256 and 512K cache sizes
    - Programmable wait states for L2 cache reads and writes
    - 2-1-1-1 read burst and zero wait state write @ 33MHz
    - No Valid bit required
   [- Supports external single-chip cache modules from thyroid-party ]
   [  vendors for high performance at 50MHz                          ]
    - Supports CPUs with L1 write-back support
o   DRAM interface:
    - Up to 128MB main memory support
    - Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM 
      modules
    - Read page hit timing of 3-2-2-2 at 33MHz
    - Supports hidden, slow. and CAS-before-RAS refresh
    - Four RAS lines to support four banks of DRAM
   [- Eight RAS lines to support four banks of DRAM  ]
    - Programmable wait states for DRAM reads and writes
   [- Programmable memory holes for supporting ISA memory ]
    - Enhanced DRAM configuration map
   [- Strong drivers on the MA lines (12/24mA) ]
   [- Supports asymmetric DRAMs                ]
o   Power management:
    - Support for SMM (System Management Mode) for system power 
      management implementations
    - Programmable power management
   [- CPU clock control ]
    - Programmable wake-up events through hardware, software, and 
      external SMI source
    - Multiple level GREEN support (NESTED_GREEN)
    - STPCLK# protocol support
   [- Programmable GREEN event timer       ](802G  only)
   [- Individually programmable peripheral ](802GP only)
o   ISA interface:
    - 100% IBM PC/AT ISA compatible
   [- Programmable edge- or level-trigger interrupts ]
    - integrates DMA, timer and interrupt controllers
   [- Slew rate control for output drivers           ]
    - Optional PS/2 style IRQ1 and IRQ12 latching
o   VESA VL interface:
    - Conforms to the VESA V2.0 specification
    - Optional support for up to two VL masters
o   Miscellaneous features:                              (802G only)
    - Full support for shadow RAM, write protection, L1/L2 
      cacheability for video, adapter, and system BIOS
    - Enhanced arbitration scheme
    - Transparent 8042 emulation for fast CPU reset and GATEA20 
      generation
o  [Miscellaneous features:                             ](802GP only)
   [- Full support for flash, write protection, L1/L2   ]
   [  cacheability for video, adapter, and system BIOS  ]
   [- Provides Micro Channel bridge support             ]
   [- 10-/16-nit I/O decodes                            ]
   [- Enhanced arbitration scheme                       ]
o   Packaging:
    - Higher integration
    - Reduced TTL count
    - Low-power, high~speed 0.8-micron CMOS technology
    - 208-pin PQFP (Plastic Quad Flat Pack)

**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91
***Notes:...
**Other:...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**FE3600/A/B/C  16/20MHz AT Chip set                              c:88
***Notes:...
***Info:...
***Configurations:...
***Features:...
**FE5300        CPU Core Logic for PS/2 Model 50/60 Compatibles   c:87...
**FE5400        CPU Core Logic for PS/2 Model 50/60 Compatibles   c:87...
**FE6500        CPU Core Logic for PS/2 Model 70/80 Compatibles   c:88...
**WD6400SX/LP   CPU Core Logic for PS/2 386SX Compatibles          <90...
**WD6500        CPU Core Logic for PS/2 386DX/486 Compatible       <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX         <11/25/91...
**WD7700/LP     System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855        System controller for 80386SX                <09/25/92...
**WD7900/LP/LV  System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110        System controller for 80386DX/486            <11/30/93...
**
**Support Chips:
**WD76C20x   Floppy, RTC, IDE and Support Logic Device       <11/25/91...
**WD76C30x   Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615     Desktop Buffer Manager                          <04/15/92...
**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
*Winbond...
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