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**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**82C556M/7M/8E  Viper-N+ Viper Notebook Chipset                  c:96
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C566/7/8     Viper-Max Chipset Scalable MultiMedia PC Solution   ?...
**82C571/572     486/Pentium                                      c:93...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
**Early Chipsets:
PCCHIP1           286/386SX Found on: M205/M209
PCCHIP2           386DX     Found on: M321
CHIP3             386DX     Seen on: a 386DX motherboard  c92
CHIP5 (4L04F1282) 386DX     Seen on: a 486DLC motherboard c92
CHIP6 (4L04F1666) [partnered with CHIP5]
CHIP11, CHIP13    486       Seen on: an isa/vlb motherboard c93

**Later Chipsets:...
*SIS...
*Symphony...
*TI (Texas Instruments)...
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers          <84
***Notes:...
***Info:
Each 'LS610  and 'LS612  memory mapper  integrated circuit  contains a
4-line to  16-line decoder, a  16-word by  12-bit RAM, 16  channels of
2-line to 1-line multiplexers, and  other miscellaneous circuitry on a
monolithic chip. Each  'LS610 also contains 12 latches  with an enable
control.

The memory  mappers are designed  to expand a  microprocessor's memory
addressing capability by  eight bits. Four bits of  the memory address
bus (see  System Block Diagram)[see  datasheet] can be used  to select
one of 16 map registers that contain  12 bits each.  these 12 bits are
presented  to the  system memory  address bus  through the  map output
buffers  along with  the  unused  memory address  bits  from the  CPU.
However, addressable memory space  without reloading the map registers
is the  same as would  be available with  the memory mapper  left out.
The  addressable  memory  space  is  increased  only  by  periodically
reloading the  map registers  from the  data bus.   This configuration
lends itself  to memory utilization  of 16 pages of  2^(n-4) registers
each  without reloading  (n -  number of  address bits  available from
CPU).

These  devices have  four modes  of operation:  read, write,  map, and
pass.  Data may be read from  or loaded into the map register selected
by  the register select  inputs (RS0  thru RS3)  under control  of R/W
whenever chip select (CS) is low. The data I/O takes place on the data
bus DO thru D7. The map  operation will output the contents of the map
register selected by the map address  inputs (MA0 thru MA3) when CS is
high and  MM (map mode control)  is low. The 'LS612  output stages are
transparent in this mode, while  the 'LS610 outputs may be transparent
or latched. When CS and MM are both high (pass mode), the address bits
on MA0 thru MA3 appear at M08-MO11, respectively (assuming appropriate
latch control) with  low levels in the other bit  positions on the map
outputs.
***Versions:...
***Features:...
**TACT82000   3-Chip 286 [no datasheet]                            c89...
**TACT82411   Snake  Single-Chip AT Controller                     c90...
**TACT82S411  Snake+ Single-Chip AT Controller [no datasheet]      c91...
**TACT83000   AT 'Tiger' Chip Set (386)                            c89...
**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91...
**Other:...
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