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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96
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**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
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**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89
***Info:
GENERAL DESCRIPTION

The W860451 is an enhanced version of the popular W860450 asynchronous
communication element  (ACE) fabricated using  WINBOND'S CMOS process.
The  device   supports  one  serial-to-parallel   conversion  on  data
characters  received  from  a  peripheral  device  or  a  MODEM.   and
parallel-to-serial  conversion on  data characters  received  from the
CPU. The  CPU can  read the complete  status of  the UART at  any time
during the functional  operation. Status information reported includes
the type and  condition of the transfer operations  being performed by
the UART as well as any error conditions (parity, overrun, framing. or
break  interrupt).   The  UART   includes  a  programmable  baud  rate
generator that is capable of dividing the timing reference clock input
by divisors of 1 to (2^16 -  1), and producing a 16x clock for driving
the internal  transmitter logic. Provisions  are also included  to use
this  16x clock  to drive  the receiver  logic.  The  UART  includes a
complete  MODEM-control capability  and a  processor-interrupt system.
interrupts can  be programmed  to the user’s  requirements, minimizing
the computing required to handle the communications link.  In addition
to its communication interface  capabilities, the W860451 provides the
user with a parallel Centronics type printer.
***Versions:...
***Features:...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
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