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**82385       32-bit Cache Controller for 80386               09/29/87
***Notes:...
***Info:
The 82385 Cache Controller is a high performance 32-bit peripheral for
Intel's 80386 Microprocessor. It  stores a copy of frequently accessed
code  and data  from main  memory  in a  zero wait  state local  cache
memory. The  82385 enables the 80386  to run at its  full potential by
reducing the  average number  of CPU wait  states to nearly  zero. The
dual  bus architecture  of the  82385 allows  other masters  to access
system resources  while the 80386  operates locally out of  its cache.
In  this situation,  the  82385's "bus  watching" mechanism  preserves
cache coherency by monitoring the  system bus address lines at no cost
to system or local throughput.

The 82385 is completely software transparent, protecting the integrity
of system  software. High performance  and board savings  are achieved
because  the  82385  integrates   a  cache  directory  and  all  cache
management logic on one chip.

1.0 82385 FUNCTIONAL OVERVIEW
Th~ 82385 Cache Controller is a high performance 32-bit peripheral for
Intel's 80386  microprocessor.  This  chapter provides an  overview of
the 82385,  and of the basic  architecture and operation  of an 80386/
82385 system.

1.1 82385 OVERVIEW

The main  function of a cache  memory system is to  provide fast local
storage  for  frequently accessed  code  and  data.  The cache  system
intercepts 80386 memory references to see if the required data resides
in the cache. If the data resides in the cache (a hit), it is returned
to the 80386 without incurring wait  states. If the data is not cached
(a  miss), the  reference  is forwarded  to  the system  and the  data
retrieved from main memory. An  efficient cache will yield a high "hit
rate" (the ratio of cache hits to total 80386 accesses), such that the
majority  of accesses  are serviced  with  zero wait  states. The  net
effect is  that the  wait states incurred  in a  relatively infrequent
miss are  averaged over  a large number  of accesses, resulting  in an
average of  nearly zero wait states  per access. Since  cache hits are
serviced locally, a  processor operating out of its  local cache has a
much  lower  "bus  utilization"  which reduces  system  bus  bandwidth
requirements, making more bandwidth available to other bus masters.

The 82385 Cache Controller integrates  a cache directory and all cache
management logic required  to support an external 32  Kbyte cache. The
cache  directory structure is  such that  the entire  physical address
range of the  80386 (4 Gigabytes) is mapped  into the cache. Provision
is made to allow areas of memory to be set aside a non-cacheable.  The
user has two  cache organization options: direct mapped  and 2-way set
associative.   Both provide  the high  hit rates  necessary to  make a
large, relatively slow  main memory array look like  a fast, zero wait
state memory to the 80386.

A  good hit  rate is  an essential  ingredient of  a  successful cache
implementation. Hit rate  is the measure ,of how  efficient a cache is
in maintaining a copy of  the most frequently requested code and data.
However,   efficiency  is   not  the   only  factor   for  performance
consideration.   Just  as   essential  are   sound   cache  management
policies.  These  policies refer  to  the  handling  of 80386  writes,
preservation  of  cache coherency,  and  ease  of  system design.  The
82385's  "posted   write"  capability  allows   80386  memory  writes,
including non-cacheable, to run with zero wait states, and the 82385's
"bus watching"  mechanism preserves cache coherency with  no impact on
system performance.  Physically, the 82385 ties directly  to the 80386
with virtually no external logic.

***Versions:...
***Features:...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series
***810         (Whitney)       04/26/99...
***810L        (Whitney)       04/26/99...
***810-DC100   (Whitney)       04/26/99...
***810e        (Whitney)       09/27/99...
***810e2       (Whitney)       01/03/01...
***815         (Solano)        06/19/00...
***815e        (Solano-2)      06/19/00...
***815em       (Solano-?)      10/23/00...
***815ep       (Solano-3)      c:Nov'00...
***815p        (Solano-3)      c:Mar'01...
***815g        (Solano-3)      c:Sep'01...
***815eg       (Solano-3)      c:Sep'01...
***820         (Camino)        11/15/99...
***820e        (Camino-2)      06/05/00...
***830M        (Almador)       07/30/01...
***830MP       (Almador)       07/30/01...
***830MG       (Almador)       07/30/01...
***840         (Carmel)        10/25/99...
***845         (Brookdale)     09/10/01...
***845MP       (Brookdale-M)   03/04/02...
***845MZ       (Brookdale-M)   03/04/02...
***845E        (Brookdale-E)   05/20/02...
***845G        (Brookdale-G)   05/20/02...
***845GL       (Brookdale-GL)  05/20/02...
***845GE       (Brookdale-GE)  10/07/02...
***845PE       (Brookdale-PE)  10/07/02...
***845GV       (Brookdale-GV)  10/07/02...
***848P        (Breeds Hill)   c:Aug'03...
***850         (Tehama)        11/20/00...
***850E        (Tehama-E)      05/06/02...
***852GM       (Montara-GM)    01/14/03...
***852GMV      (Montara-GM)    ???...
***852PM       (Montara-GM)    06/11/03...
***852GME      (Montara-GM)    06/11/03...
***854         (?)             04/11/05...
***855GM       (Montara-GM)    03/12/03...
***855GME      (Montara-GM)    03/12/03...
***855PM       (Odem)          03/12/03...
***860         (Colusa)        05/21/01...
***865G        (Springdale)    05/21/03...
***865PE       (Springdale-PE) 05/21/03...
***865P        (Springdale-P)  05/21/03...
***865GV       (Springdale-GV) c:Sep'03...
***875P        (Canterwood)    04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96
***Info:...
***Configurations:...
***Features:
o   Supports Intel Pentium CPU and other compatible CPU at 
    75/66/60/50MHz (external clock speed)
o   Supports the Pipelined Address Mode of Pentium CPU
o   Supports the Full 64-bit Pentium Processor data Bus
o   Supports 32-bit PCI Interface
o   Integrated Second Level (L2) Cache Controller
    - Write Through and Write Back Cache Modes
    - 8 bits or 7 bits Tag with Direct Mapped Cache Organization
    - Integrated 16K bits Dirty Ram
    - Supports Pipelined Burst SRAM
    - Supports 256 KBytes to 512 MBytes Cache Sizes
    - Cache Read/Write Cycle of 3-1-1-1-1-1-1-1 at 66 MHz
o   Integrated DRAM Controller
    - Supports 3 Banks of FP/EDO SIMMs, or 2 Banks of SDRAM DIMMs
    - Supports 2Mbytes to 384Mbytes of main memory
    - Supports 256K/512K/1M/2M/4M/16M x N FP/EDO/SDRAM DRAM
    - Supports 3V or 5V DRAM.
    - Supports Symmetrical and Asymmetrical DRAM.
    - Supports 32 bits/64 bits mixed mode configuration
    - Supports Concurrent Write Back for FP/EDO DRAM
    - Supports Mixed DRAM (FP/EDO/SDRAM) Technology
    - Supports CAS before RAS Refresh
    - Supports Relocation of System Management Memory
    - Programmable CAS# ,RAS#, RAMW# and MA Driving Current
    - Fully Configurable for the Characteristic of Shadow RAM (640 
      KBytes to 1 MBytes)
    - Supports FP DRAM 5-3-3-3(-3-3-3-3) Burst Read Cycles
    - Supports EDO DRAM 4/5-2-2-2(-2-2-2-2) Burst Read Cycles
    - Supports SDRAM 6/7-1-1-1(-2-1-1-1) Burst Read Cycles
    - Supports X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
    - Supports 8 Qword Deep Buffer for Read/Write Reordering, Dword 
      Merging and 3/2-1-1-1 Post write Cycles
    - Two Programmable Non-Cacheable Regions
    - Option to Disable Local Memory in Non-Cacheable Regions
    - Shadow RAM in Increments of 16 KBytes
o   Integrated PMU Controller
    - Supports SMM Mode of CPU
    - Supports CPU Stop Clock
    - Supports Break Switch
    - Supports Modem Ring Wakeup
    - Supports Automatic Power Supply Control
o   Provides High Performance PCI Arbiter.
    - Supports 3 internal masters and 5 external  PCI Masters
    - Supports Rotating Priority Mechanism
    - Hidden Arbitration Scheme Minimizes Arbitration Overhead.
    - Supports Concurrency between CPU to Memory and PCI to PCI.
o   Integrated Host-to-PCI Bridge
    - Supports Asynchronous/Synchronous PCI Clock
    - Translates the CPU Cycles into the PCI Bus Cycles
    - Provides CPU-to-PCI Read Assembly and Write Disassembly 
      Mechanism
    - Translates Sequential CPU-to-PCI Memory Write Cycles into PCI 
      Burst Cycles
    - Zero Wait State Burst Cycles
    - Supports 8 DW Deep Buffer for CPU-to-PCI Posted Write Cycles
    - Supports Pipelined Process in CPU-to-PCI Access
    - Supports Advance Snooping for PCI Master Bursting
    - Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
    - Fast back-to-back
o   Integrated Posted Write Buffers and Read Prefetch Buffers to 
    Increase System Performance
    - CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep, Always 
      Sustains 0 Wait Performance on CPU-to-Memory.
    - CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
    - PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep, Always 
      Streams 0 Wait Performance on PCI-to/from-Memory Access
    - PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
o   Built-in one 32-bit General Purpose Register
o   Integrated PCI-to-ISA Bridge
    - Translates PCI Bus Cycles into ISA Bus Cycles
    - Translates ISA Master or DMA Cycles into PCI Bus Cycles
    - Provides a Dword Post Buffer for PCI to ISA Memory cycles
    - Two 32 bit Prefetch/Post Buffers Enhance the DMA and ISA Master 
      Performance
    - Fully Compliant to PCI 2.1
o   Enhanced DMA Functions
    - 8-, 16- bit DMA Data Transfer
    - ISA compatible, and Fast Type F DMA Cycles
    - Two 8237A Compatible DMA Controllers with Seven Independent 
      Programmable Channels
    - Provides the Readability of the two 8237 Associated Registers
o   Built-in Two 8259A Interrupt Controllers
    - 14 Independently Programmable Channels for Level- or Edge-
      triggered Interrupts
    - Provides the Readability of the two 8259A Associated Registers
o   Three Programmable 16-bit Counters compatible with 8254
    - System Timer Interrupt
    - Generates Refresh Request
    - Speaker Tone Output
    - Provides the Readability of the 8254 Associated Registers
o   Built-in Keyboard Controller
    - Hardwired Logic Provides Instant Response
    - Supports PS/2 Mouse
    - Support Hot Key "Sleep" Function
o   Built-in Real Time Clock(RTC) with 256B CMOS SRAM
o   Fast PCI IDE Master/Slave Controller
    - Fully Compatible with PCI Local Bus Specification V2.1
    - Supports PCI Bus Mastering
    - Plug and Play Compatible
    - Supports Scatter and Gather
    - Supports Dual Mode Operation - Native Mode and 
      Compatibility Mode
    - Supports IDE PIO Timing Mode 0, 1, 2 of ANSI ATA Specification
    - Supports Mode 3 and Mode 4 Timing Proposal on Enhanced IDE 
      Specification
    - Supports Multiword DMA Mode 0, 1, 2
    - Separate IDE Bus
    - Two 8x32-bit FIFO for PCI Burst Read/Write Transfers.
o   Universal Serial Bus Controller
    - Host/Hub Controller
    - Two USB ports
o   On-Board Plug and Play Support
    - One Steerable DMA Channel
    - One Steerable Interrupt
    - One Programmable Chip Select
o   Supports the Reroutibility of the four PCI Interrupts
o   Supports Flash ROM
o   480-Pin BGA Package
o   0.5 μm CMOS Technology

**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

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