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**What's not included:
All  information included  in  this  file can  be  referenced to  some
document or  picture.  Or at least  should be:-) As a  result of this,
proprietary chip sets, and odd combinations of different chip sets are
not  usually  included.   There  tends  to  be  scant  information  on
proprietary chip sets, i.e.  no  datasheet.  Similarly chip sets built
using some components  from one manufacture and some  from another are
kind of difficult to deal with.

An example  I know of  is a  25 MHz 386  DX motherboard that  uses the
Intel N82230/N82231  (formerly, ZyMOS)  286 chip  set, with  an AUStek
cache Controller.   I know it  existed but there is  no documentation.
So the best I can say you'll have  to take my word that it existed.  I
can't include it because there is no real information there.

Also  not  included  is  anything  that  isn't  a  PC-compatible  chip
set.  I.e.  no Macintosh  info.  Any Information  on PC-incompatibles/
pseudo-compatibles, and  other weirdi-type  stuff I have  a particular
interest in.  See  the section: 'Info needed on'.  Some information on
video  chip  sets  is  included,  occasionally but  the  focus  is  on
motherboard implementation.

**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96
***Info:...
***Configurations:...
***Features:
o   Supports Intel Pentium CPU and other compatible CPU at 
    75/66/60/50MHz (external clock speed)
o   Supports the Pipelined Address Mode of Pentium CPU
o   Supports the Full 64-bit Pentium Processor data Bus
o   Supports 32-bit PCI Interface
o   Integrated Second Level (L2) Cache Controller
    - Write Through and Write Back Cache Modes
    - 8 bits or 7 bits Tag with Direct Mapped Cache Organization
    - Integrated 16K bits Dirty Ram
    - Supports Pipelined Burst SRAM
    - Supports 256 KBytes to 512 MBytes Cache Sizes
    - Cache Read/Write Cycle of 3-1-1-1-1-1-1-1 at 66 MHz
o   Integrated DRAM Controller
    - Supports 3 Banks of FP/EDO SIMMs, or 2 Banks of SDRAM DIMMs
    - Supports 2Mbytes to 384Mbytes of main memory
    - Supports 256K/512K/1M/2M/4M/16M x N FP/EDO/SDRAM DRAM
    - Supports 3V or 5V DRAM.
    - Supports Symmetrical and Asymmetrical DRAM.
    - Supports 32 bits/64 bits mixed mode configuration
    - Supports Concurrent Write Back for FP/EDO DRAM
    - Supports Mixed DRAM (FP/EDO/SDRAM) Technology
    - Supports CAS before RAS Refresh
    - Supports Relocation of System Management Memory
    - Programmable CAS# ,RAS#, RAMW# and MA Driving Current
    - Fully Configurable for the Characteristic of Shadow RAM (640 
      KBytes to 1 MBytes)
    - Supports FP DRAM 5-3-3-3(-3-3-3-3) Burst Read Cycles
    - Supports EDO DRAM 4/5-2-2-2(-2-2-2-2) Burst Read Cycles
    - Supports SDRAM 6/7-1-1-1(-2-1-1-1) Burst Read Cycles
    - Supports X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
    - Supports 8 Qword Deep Buffer for Read/Write Reordering, Dword 
      Merging and 3/2-1-1-1 Post write Cycles
    - Two Programmable Non-Cacheable Regions
    - Option to Disable Local Memory in Non-Cacheable Regions
    - Shadow RAM in Increments of 16 KBytes
o   Integrated PMU Controller
    - Supports SMM Mode of CPU
    - Supports CPU Stop Clock
    - Supports Break Switch
    - Supports Modem Ring Wakeup
    - Supports Automatic Power Supply Control
o   Provides High Performance PCI Arbiter.
    - Supports 3 internal masters and 5 external  PCI Masters
    - Supports Rotating Priority Mechanism
    - Hidden Arbitration Scheme Minimizes Arbitration Overhead.
    - Supports Concurrency between CPU to Memory and PCI to PCI.
o   Integrated Host-to-PCI Bridge
    - Supports Asynchronous/Synchronous PCI Clock
    - Translates the CPU Cycles into the PCI Bus Cycles
    - Provides CPU-to-PCI Read Assembly and Write Disassembly 
      Mechanism
    - Translates Sequential CPU-to-PCI Memory Write Cycles into PCI 
      Burst Cycles
    - Zero Wait State Burst Cycles
    - Supports 8 DW Deep Buffer for CPU-to-PCI Posted Write Cycles
    - Supports Pipelined Process in CPU-to-PCI Access
    - Supports Advance Snooping for PCI Master Bursting
    - Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
    - Fast back-to-back
o   Integrated Posted Write Buffers and Read Prefetch Buffers to 
    Increase System Performance
    - CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep, Always 
      Sustains 0 Wait Performance on CPU-to-Memory.
    - CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
    - PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep, Always 
      Streams 0 Wait Performance on PCI-to/from-Memory Access
    - PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
o   Built-in one 32-bit General Purpose Register
o   Integrated PCI-to-ISA Bridge
    - Translates PCI Bus Cycles into ISA Bus Cycles
    - Translates ISA Master or DMA Cycles into PCI Bus Cycles
    - Provides a Dword Post Buffer for PCI to ISA Memory cycles
    - Two 32 bit Prefetch/Post Buffers Enhance the DMA and ISA Master 
      Performance
    - Fully Compliant to PCI 2.1
o   Enhanced DMA Functions
    - 8-, 16- bit DMA Data Transfer
    - ISA compatible, and Fast Type F DMA Cycles
    - Two 8237A Compatible DMA Controllers with Seven Independent 
      Programmable Channels
    - Provides the Readability of the two 8237 Associated Registers
o   Built-in Two 8259A Interrupt Controllers
    - 14 Independently Programmable Channels for Level- or Edge-
      triggered Interrupts
    - Provides the Readability of the two 8259A Associated Registers
o   Three Programmable 16-bit Counters compatible with 8254
    - System Timer Interrupt
    - Generates Refresh Request
    - Speaker Tone Output
    - Provides the Readability of the 8254 Associated Registers
o   Built-in Keyboard Controller
    - Hardwired Logic Provides Instant Response
    - Supports PS/2 Mouse
    - Support Hot Key "Sleep" Function
o   Built-in Real Time Clock(RTC) with 256B CMOS SRAM
o   Fast PCI IDE Master/Slave Controller
    - Fully Compatible with PCI Local Bus Specification V2.1
    - Supports PCI Bus Mastering
    - Plug and Play Compatible
    - Supports Scatter and Gather
    - Supports Dual Mode Operation - Native Mode and 
      Compatibility Mode
    - Supports IDE PIO Timing Mode 0, 1, 2 of ANSI ATA Specification
    - Supports Mode 3 and Mode 4 Timing Proposal on Enhanced IDE 
      Specification
    - Supports Multiword DMA Mode 0, 1, 2
    - Separate IDE Bus
    - Two 8x32-bit FIFO for PCI Burst Read/Write Transfers.
o   Universal Serial Bus Controller
    - Host/Hub Controller
    - Two USB ports
o   On-Board Plug and Play Support
    - One Steerable DMA Channel
    - One Steerable Interrupt
    - One Programmable Chip Select
o   Supports the Reroutibility of the four PCI Interrupts
o   Supports Flash ROM
o   480-Pin BGA Package
o   0.5 μm CMOS Technology

**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?
***Notes:...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

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