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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
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**VL82C486         Single-Chip 486, SC486, Controller                ?
***Basics:...
***Info:

The VL82C486 is a Single-Chip High Performance Controller for 486- and
486SX/487SX- based PC/AT systems.

The VL82C486  includes the  dual 82C37A  DMA controllers,  dual 82C59A
programmable  int-  errupt  controllers, 82C54  programmable  interval
timer, 82284 clock and ready gener- ator, 82288 bus controller and the
logic  for  address/data  bus  control, memory  cont-  rol,  shutdown,
refresh generation and refresh/DMA arbitration.

The  VL82C486  Controller   is  designed  to  perform   in  486DX-  or
486SX/487SX-based PC/AT- compatible systems running  up to 33 MHz. The
VL82C486 replaces the following devices on the motherboard:
o  Two 82C37A DMA controllers
o  Two 82C59A interrupt controllers
o  82C54 timer
o  74LS612 memory mapper
o  82284 clock generator and ready interface
o  82288 bus controller

The controller also includes the following:
o  Memory/refresh controller
o  Port B and NMI logic
o  Bus steering logic
o  Turbo Mode control logic
o  Parity checking logic
o  Parity generation logic
o  Support for Weitek numeric coprocessors.

The memory controller logic is capable of accessing up to 64 MB. There
can be up to four banks of 256K, 1M, or 4M DRAMs used in a system. The
VL82C486  can drive  four banks  without external  buffering. Built-in
Page  Mode operation  and up  to four-way  interleaving allows  the PC
designer   to   maximize   system   perform-   ance   using   low-cost
DRAMs.  Programmable DRAM  timing  is provided  for  RAS pre-  charge,
RAs-to-CAS delay, and CAS pulse width.

Shadowing features are  supported on 16K boundarys  between A0000h and
FFFFFh (640 KB  to 1 MB). simultaneous use of  shadowed ROM and direct
system  board   access  is  possible  in   a  non-overlapping  fashion
throughout  this memory  space. Control  over four  access options  is
provided:

1. Access ROM or slot bus for reads and writes.
2. Access system board DRAM for reads and writes.
3. Access system board DRAM for reads and slot bus for writes.
4. Shadow setup mode. Read ROM of slot bus, write system board DRAM.

A special mode is supported for erasing and programming flash memories
for the case where such devices are used as the BIOS ROMs.

Three special programmable address  regions are provided. The fast-bus
clock reg- ion  allows accesses to certain memory regions  at a faster
ISA  bus  clock  rate  for  fast  on-board  or  off-board  devices.  A
Non-Cacheable Region and/or a Write-Pro-  tected Region may be defined
by a set of six registers that allow  memory in the region 640 KB to 1
MB to be marked as  non-cacheable and/or write-protected in increments
of 16 KB. A further set of registers allows a memory range anywhere in
the first 64  MB of memory to be  marked as a DRAM region,  an ISA bus
region, or  a local  bus region, either  cachable or  non-cacheable in
increments of 2 KB. 64 KB, or 1 MB.

Further  support for  devices  that reside  on the  486  local bus  is
provided  through use  of the  -LBA  (Local Bus  Access) input,  which
deselects  the  VL82C486  during  CPU cycles.  Also,  a  memory  range
anywhere in  the first  64 MB of  memory can be  program- med  via the
internal Mapping  Registers to  make the VL82C486  access a  local bus
dev-  ice  as a  486  bus  memory device  during  DMA  or Master  Mode
transfers.

The VL82C486 handles  system board refresh directly  ans also controls
the  timing  of  slot  bus   refresh.  Refresh  may  be  performed  in
Synchronous, Asynchronous or Decoupled  Mode. In the Synchronous Mode,
slot bus and  on-board DRAM refresh cycles  proceed simultaneously and
all  memory cycles  are held  until  both have  completed. The  Async-
hronous  Mode  allows in-  and  off-board  refreshes to  be  initiated
simultaneously, but to complete asynchronously, allowing sooner access
to DRAM. In the Decoupled Mode, a separate refresh counter is used for
slot  bus refresh,  allowing  on-board DRAM  and  system refreshes  to
proceed independently,  with DRAM refreshes initiated  during bus idle
cycles.  CAS-before-RAS  refresh  is  also  supported.  Refreshes  are
staggered to minimize power supply  loading and attenuate noise on the
VDD and ground pins. The  VL82C486 supports the standard PC/AT refresh
period of 15.625 us as well as 125 us.

Support for  write-through cache  controllers is provided  through the
use of a -MISS pin to detect cache-hits and cache-misses.

The interrupt controller  logic consists of two  82C59A megacells with
eight inter- rupt request lines each for a total of 16 interrupts. The
two megacells are  cascaded internally and two [sic]  of the interrupt
request inputs are connected to internal circuitry allowing a total of
13 external interrupt requests.  There  is special progr- amable logic
included in the VL82C486 which allows deglitching of inputs on all the
interrupt request pins.

The  interval timer  includes  one 82C54  counter/timer megacell.  The
counter/timer   has  three   independent  16-bit   counters  and   six
programmable counter modes.

The  DMA  controllers  are   82C37A  compatible.  Each  controls  data
transfers between an I/O channel and  on- or off-board memory. DMA can
transfer data over the full 64  MB range available. there are Internal
latches provided  for latching the  middle address bits output  by the
82C37A megacells on  the data bus, and the 74LS612  memory mappers are
provided to generate the upper address bits.

The VL82C486 can be programmed to generate the ISA bus timing from the
CPU clock oscillator or a separate asynchronous oscillator.

The  VL82C486 also  performs  all the  data  buffer control  functions
required for a  486XX processor-based PC/AT system.  Under the control
of the CPU, the VL82C486 routes data  to and from the CPU's D bus, the
internal XD bus, and the slots (SD bus). During CPU ISA bus reads, the
data is  latched for synchronization  with the CPU. Parity  is checked
for D bus DRAM read operations.  The chip does not generate parity for
CPU writes to DRAM.

***Configurations:...
***Features:...
**VL82C425         486 Cache controller                              ?...
**????????         Cheetah 486, PCI [no datasheet]                   ?...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
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