[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94
***Info:...
***Versions:...
***Features:
o VL to PCI Bridge
- Combined with VT82C486 or VT82C496G for 80486SX/DX/DX2/DX4 based
PCI/VL/ISA Green-PC systems
- Combined with VT82C530MV chip set for Pentium/P54C/M1 based
PCI/VL/ISA Green-PC Systems
o Sophisticated Bridging Capabilities
- Supports PCI master to PCI slave cycles
- Supports PCI master to VL bus slave, system memory and ISA
slave cycles
- Supports VL master including CPU to PCI slave cycles
- Supports ISA master to VL or PCI slave cycles
- Supports multiple accelerated decoding schemes from VL master
including CPU to PCI and ISA slaves
- Supports CPUs with write-back level-one cache
- Concurrent CPU and PCI operation
- 4 level of CPU/VL to PCI post write buffers
- Automatic detection of data streaming burst cycles from CPU/VL
to PCI bus
- 4 level of post write buffers from PCI master to VL slave,
system memory and ISA slaves
- 4 level of prefetch buffers from system memory for access by PCI
masters
- Bursting capability for both PCI and CPU/VL bus
o Intelligent PCI Interface
- PCI 2.0 compliant
- Synchronous or divide-by-two CPU clock
- Hidden arbitration for up to four PCI masters
- Supports PCI preemption and time-out function
- Supports PCI master and slave initiated abort mechanism
- Supports PCI lock function
- Supports data parity generation for PCI master read cycles
- Supports data parity checking for PCI master write cycles
- Supports parity error and system error reporting on the PCI bus
- Supports PCI configuration cycles
- Interrupt steering and conversion to edge triggering for ISA
compatibility
o PCI Compliant IO Characteristics
o 0.8um high speed and low power CMOS process
o 160pin PQFP package
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved