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**'chip set', 'chip-set' or 'chipset'?
I don't  know, all seem  to be ok/OK/okay. CHIPset  is a term  used by
C&T.

**What's not included:
All  information included  in  this  file can  be  referenced to  some
document or  picture.  Or at least  should be:-) As a  result of this,
proprietary chip sets, and odd combinations of different chip sets are
not  usually  included.   There  tends  to  be  scant  information  on
proprietary chip sets, i.e.  no  datasheet.  Similarly chip sets built
using some components  from one manufacture and some  from another are
kind of difficult to deal with.

An example  I know of  is a  25 MHz 386  DX motherboard that  uses the
Intel N82230/N82231  (formerly, ZyMOS)  286 chip  set, with  an AUStek
cache Controller.   I know it  existed but there is  no documentation.
So the best I can say you'll have  to take my word that it existed.  I
can't include it because there is no real information there.

Also  not  included  is  anything  that  isn't  a  PC-compatible  chip
set.  I.e.  no Macintosh  info.  Any Information  on PC-incompatibles/
pseudo-compatibles, and  other weirdi-type  stuff I have  a particular
interest in.  See  the section: 'Info needed on'.  Some information on
video  chip  sets  is  included,  occasionally but  the  focus  is  on
motherboard implementation.

**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory  bus controller, provide a second-level
cache  subsystem  that eliminates  the  memory  latency and  bandwidth
bottleneck for  a wide  range of multiprocessor  systems based  on the
i860 XP  microprocessor. The CPU  interface is optimized to  serve the
i860  XP microprocessor  with zero  wait  states at  up to  50 MHz.  A
secondary cache  built from the  82495XP and 82490XP isolates  the CPU
from  the memory subsystem;  the memory  can run  slower and  follow a
different protocol than the i860 XP microprocessor.
         
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...