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**CS82310  PEAK/DM 386 AT           (82C351/82C355/82C356)         c91
***Info:
The CS82310 PEAK/DM CHIPSet is a three chip VLSI implementation of the
systems logic required  to implement a cache-based  386DX system. This
CHIPSet  is  designed to  offer  a  100% PC/AT  compatible  Integrated
solution. The  flexible architecture  of the PEAK/DM  allows it  to be
used in any iAPX386-based system  design such as CAD/CAE workstations,
office  systems, industrial  and financial  transaction systems.   The
CS82310 PEAK/DM CHIPSet provides a  complete cache based 386/AT system
using only  19 components  plus memory  devices.  The  CS82310 PEAK/DM
CHIPSet consists  of one 82C351 CPU/cache/DRAM  controller, one 82C355
data  buffer,  and  one  82C356 peripheral  controller.   The  CHIPSet
supports a local CPU bus, a 32-bit memory bus, and AT buses.

82C351 CPU/Cache/D RAM/Controller
By integrating both the cache  and DRAM control functions in one chip,
the  82C351  supports  simultaneous   activation  of  cache  and  DRAM
accesses; minimizing  the cache miss penalty. It  has hardware support
to allow  the user to  designate up to  four blocks (of  variable size
from 4KB  to 4MB) of main  memory as non-cacheable  address space. The
82C351 cache  controller supports  a direct mapped  cache architecture
and cache sizes  of 32KB, 64KB, 128KB, or  256KB. Memory write updates
are implemented using a  buffered write-through scheme.  The 82C351 is
available in a 160-pin PFP package.

82C355 Data Buffer
The 82C355 bus controller contains  the data buffers used to interface
the local and system  memory buses and a path for the  AT data bus. In
addition  to   having  high  current  bus  drive,   it  also  performs
conversions between the different sized data paths and provides parity
generation  and checking.  The 82C355  is available  in a  120-pin PFP
package.

82C356 Peripheral Controller
The 82C356 peripheral controller  contains the address buffers used to
interface between  the processor address bus (A<23:2>)  and the system
address  bus  (SA<19:0>).   It  also  contains  an  equivalent  82C206
integrated  peripheral  controller  that  incorporates: two  8237  DMA
controllers, two  8259 interrupt controllers,  one 8254 timer/counter,
one  MC146818 real  time clock,  and several  TTL/SSI  interface logic
chips.

***Configurations:...
***Features:...
**CS8281   NEATsx (386SX)           (82C811/812/215/206)       c:Dec89...
**CS8283   LeAPset-sx               (82C841/82C242/82C636)     c:Mar90...
**CS8285   PEAKsx                   (82C836/82C835)                c91...
**CS8288   CHIPSlite-sx             (82C836/82C641/82C835)          c?...
**CS4000   WinCHIPS                 (64200/84021/84025)            c92...
**CS4021   ISA/486                  (84021/84025)                  c92...
**CS4031   CHIPSet                  (84031/84035)              5/10/93...
**CS4041/5 CHIPSet                  (84041/84045)              2/10/95...
**CB8291   ELEAT                    [no datasheet]                 c90...
**CB8295   ELEATsx                  [no datasheet]                 c90...
**82C100   IBM PS/2 Model 30/Super XT                                ?...
**82C110   IBM PS/2 Model 30/Super XT                                ?...
**82C235   Single Chip AT (SCAT)                                   c89...
**82C836   Single Chip 386sx (SCATsx)                              <91...
**F8680/A  PC/CHIP Single-Chip PC                                  c93...
**
**Support Chips:
**64200    (Wingine) High Performance 'Windows Engine'         c:Oct91...
**82C206   Integrated Peripheral Controller                        c86...
**82C601/A Single Chip Peripheral Controller                 <08/30/90...
**82C607   Multifunction Controller                             <Jun88...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
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**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


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