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**440 series:
***440FX (Natoma)       05/06/96...
***440LX (Balboa)       08/27/97...
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***440ZX & 440ZX-66 (?) 01/04/99...
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**VL82C480         System/Cache/ISA bus Controller                   ?
***Info:...
***Configurations:...
***Features:
o   Fully compatible with 486-based ISA bus systems
o   Power-on reset option selects various operational modes
o   Up to 40 MHz CPU operation
o   Replaces the following peripheral logic on the motherboard:
    - Two 82C37A DMA controllers
    - 74LS612 memory mappers (extended to support 64 MB)
    - Two 82C59A interrupt controllers
    - 82C54 timer
    - 82284 clock generator and ready interface
    - 82288 bus controller
o   Memory controller features include:
    - Up to 64 MB system memory
    - 256K, 1M or 4M DRAM
    - Double-sided SIMMs
    - Page Mode DRAM access
    - Two-way interleave support
    - Programmable RAS#/CAS# timing
    - Burst read and write support
    - Parity generation/checking for on-board DRAM
    - Staggered RAS# refresh
o   Supports:
    - One to four banks 32 bits wide
    - 8- or 16-bit wide BIOS ROM
    - shadow RAM in the 640K-1M area
    - Asynchronous ISA bus operation up to 16 MHz
    - Relocation of slot ROMs
    - Access to devices residing on the local bus
    - Weitek 4167 numeric coprocessor
o   0.8-micron CMOS technology
o   208-lead MQFP (metric quad flat pack)
o   Includes:
    - Memory/refresh controller
    - Port A, B, and NMI logic
    - Bus steering logic
    - Turbo control
    - hidden refresh
    - Three-stateable outputs for board testing
o   Selectable slow DRAM refresh saves power
o   On-chip write-back cache controller:
    - External tags
    - Direct map
    - Separate "dirty" RAM not required
    - 2-1-1-1 reads with two banks, 2-2-2-2 with one bank
    - 32 KB to 1MB cache size
    - One wait state writes on cache-hits
    - Optional zero wait state writes
    - Optional one wait state reads
o   Other features:
    - Programmable for 10- or 16-bit internal I/O addressing
    - Programmable drive on the DRAM and ISA bus signals
    - Programmable memory access to define "fast-bus", local bus, slot
      bus, non-cacheable and write-protect areas
    - Input pin defines access to local bus devices

**VL82C481         System/Cache/ISA bus Controller                 c92...
**VL82C486         Single-Chip 486, SC486, Controller                ?...
**VL82C425         486 Cache controller                              ?
***Info:...
***Versions:...
***Features:...
**????????         Cheetah 486, PCI [no datasheet]                   ?...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
**Video: ...
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**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...