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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


**?????  (Profusion)    c:99...
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**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97
***Info:
The VT82C596 MPIPC (Mobile  PCI Integrated Peripheral Controller) is a
high   integration,  high   performance,  power-efficient,   and  high
compatibility device that supports Intel and non-Intel based processor
to  PCI  bus  bridge   functionality  to  make  a  complete  Microsoft
PC97-compliant PCI/ISA  system. In addition to  complete ISA extension
bus   functionality,  the   VT82C596  includes   standard  intelligent
peripheral controllers:

a) Master  mode enhanced IDE  controller with dual channel  DMA engine
and  interlaced dual  channel  commands. Dedicated  FIFO coupled  with
scatter  and  gather master  mode  operation  allows high  performance
transfers between PCI and IDE devices. In addition to standard PIO and
DMA  mode  operation,  the  VT82C596  also  supports  the  UltraDMA-33
standard  to  allow  reliable  data  transfer  rates  up  to  33MB/sec
throughput.  The  IDE  controller  is  SFF-8038i  v1.0  and  Microsoft
Windows- 95 compliant.

b) Universal Serial Bus controller  that is USB v1.0 and Universal HCI
v1.1 compliant. The  VT82C596 includes the root hub  with two function
ports with integrated physical  layer transceivers. The USB controller
allows hot  plug and play  and isochronous peripherals to  be inserted
into  the system with  universal driver  support. The  controller also
implements legacy  keyboard and mouse support so  that legacy software
can run transparently in a non-USB-aware operating system environment.

c) Keyboard controller with PS2 mouse support.

d) Real  Time Clock with  256 byte extended  CMOS. In addition  to the
standard ISA  RTC functionality, the integrated RTC  also includes the
date alarm,  century field,  and other enhancements  for compatibility
with   the  ACPI   standard.   

e) Notebook-class  power management functionality compliant  with ACPI
and legacy APM requirements.  Multiple sleep states (power-on suspend,
suspend-to-DRAM,  and  suspend-to-Disk)  are supported  with  hardware
automatic   wake-up.    Additional    functionality   includes   event
monitoring, CPU clock throttling  and stop (Intel processor protocol),
PCI bus clock stop control,  modular power, clock and leakage control,
hardware-based and software-based event handling, general purpose I/O,
chip select and external SMI.

f) Full System Management Bus (SMBus) interface.

g) Distributed DMA  capability for support of ISA  legacy DMA over the
PCI  bus. PC/PCI  and Serial  IRQ  mechanisms are  also supported  for
docking and non-docking applications.

h) Plug and  Play controller that allows complete  steerability of all
PCI interrupts  to any  interrupt channel. Three  additional steerable
interrupt  channels   are  provided  to   allow  plug  and   play  and
reconfigurability of on-board peripherals for Windows 95 compliance.

i)  External IOAPIC interface  for Intel-compliant  symmetrical multi-
processor systems.

The  VT82C596 also  enhances  the functionality  of  the standard  ISA
peripherals.  The integrated interrupt  controller supports  both edge
and level triggered interrupts  channel by channel. The integrated DMA
controller  supports  type F  DMA  in  addition  to standard  ISA  DMA
modes. Compliant with the PCI-2.1 specification, the VT82C596 supports
delayed transactions so  that slower ISA peripherals do  not block the
traffic  of  the PCI  bus.  Special circuitry  is  built  in to  allow
concurrent operation  without causing dead  lock even in  a PCI-to-PCI
bridge environment. The chip  also includes eight levels (doublewords)
of line  buffers from the  PCI bus to  the ISA bus to  further enhance
overall system performance.

***Versions:...
***Features:...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
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