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*ACC Micro...
**Other chips
ACC1200   Clock synthesizer Supports Pentium-Pro and Pentium-class PCI
ACC16C451 Multi I/O 1x16450/1xLPT
ACC16C452 Multi I/O 2x16450/1xLPT
ACC16C461 Multi I/O 1x16450/1xLPT
ACC2042   Keyboard/Mouse Controller
ACC2188   PCI bus controller  Support 32-bit PCI Bus interface with built-in power management control and synchronous / asynchronous clock feature. 
ACC3201   PC/XT/AT FDD Controller
ACC3202   PS/2 FDD Controller
ACC3203   PS/2 FDD Controller
ACC3211   PC AT/XT FDD Controller (x4) + with IDE
ACC3221   Multi I/O Controller, floppy/IDE/2x16450/1xLPT
ACC3223   Multi I/O Controller, floppy/IDE/2x16550/1xLPT
ACC3350   Ultra SCSI 
ACC3360   UltraWide SCSI 
ACC3618   3D surround controller ISA
ACC5810   Micro Channel Interface Chip
ACC808 	  Plug-and-Play Controller
ACC????   Manhattan PCI-based FireWire for Pentium
ACC????   Memphis PCI-based CardBus and FireWire

*ALD...
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*AMD . . . . . . . [no datasheets, some info]...
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*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:
o   High Performance Second Level Cache
    - Zero Wait States at 66 MHz 
    - Two-Way Set Associative 
    - Writeback with MESI Protocol 
    - Concurrent CPU Bus and Memory Bus Operation 
    - Boundary Scan
o   Pentium Processor (735\90, 815\100)
    - Chip Set Version of Pentium Processor (735\90, 815\100) 
    - Superscalar Architecture -
    - Enhanced Floating Point 
    - On-Chip 8K Code and 8K Data Caches
    - See Pentium Processor Family Data Book for More Information
o   Highly Flexible
    - 256K to 512K with Parity
    - 32-, 64-, or 128-Bit Wide Memory Bus
    - Synchronous, Asynchronous and Strobed Memory Bus Operation
    - Selectable Bus Widths, Line Sizes, Transfers and Burst Orders
o   Full Multiprocessing Support
    - Concurrent CPU, Memory Bus and Snoop Operations
    - Complete MESI Protocol
    - Internal/External Parity Generation/Checking
    - Supports Read For Ownership, Write-Allocation and Cache-to-Cache
      Transfers

**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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