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**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C546/547 Python PTM3V c:94
***Notes:...
***Info:
The OPTi Python Chipset provides a highly integrated solution for
fully compatible, high-performance PC/AT platforms. Together, with
OPTi's 82C206 Integrated Peripheral Controller (IPC), this chipset
will support the Pentium processor in the most cost effective and
feature-rich designs available today. This highly integrated approach
provides the foundation for a cost effective platform without
compromising performance. The OPTi Python Chipset supplies a powerful
solution positioned to deliver value without neglecting quality,
compatibility, or reliability.
The Python Chipset is comprised of two chips, the 82C547 System
Controller (SYSC) and the 82C546 AT Bus Controller (ATC). A complete
Pentium processor solution consists of the Python Chipset and the
82C206 Integrated Peripheral Controller (IPC).
82C546 (ATC) AT Bus Controller
The 82C546 ATC integrates the AT bus interface and data buffers for
transfers between the CPU data bus, local data bus and the DRAM data
bus. It also provides the ISA to local bus command translation.
o 208-pin PQFP
o Data bus buffer (host data to memory data)
o Data bus buffer control (ISA to memory)
o Parity generation and detection circuitry
o Keyboard controller chip select
o Local bus interface (ISA to local bus command translation)
82C547 (SYSC) System Controller
The 82C547 SYSC provides the control functions for the host CPU
interface, the 32-bit local bus interface, the 64-bit Level 2 (12)
cache and the 64-bit DRAM bus. The SYSC also controls the data flow
between the CPU bus, the DRAM bus, the local bus, and the 8/16-bit ISA
bus.
o 160-pin PQFP
o Pentium CPU interface
o DRAM controller
o L2 cache controller
o Ll cache controller
o Local bus interface
o Reset generation
o Arbitration logic
o Data bus buffer control (memory data to/from host data)
o Extended DMA page register
o Keyboard emulation of A20M# and CPU warm reset
o Port B and Port 92h Register
82C206 (IPC) Integrated Peripherals Controller
The 82C206 IPC provides two DMA controllers, two interrupt control-
lers, one timer/counter, and a real-time clock in an industry standard
single-chip solution for the peripherals attached to the PC/AT
peripheral bus.
o 84-pin PLCC or 100-pin PQFP
o Supports four DMA transfer modes
o Special Commands provided for ease of programming
Support Chips
The 82C606A and 82C606B are two buffer/translation devices used to
translate 3.3V signals to 5.0V signal levels in Python motherboard
solutions. These devices buffer the CPU address bus to the ISA and VL
address buses, the 82C546 ATC's memory data bus to the ISA data bus,
the peripheral XD bus to the ISA SA and SD buses. The 82C606A and
82C606B integrate a number of glue logic TTL devices (approximately
eleven), hence reducing the amount of TTL on the motherboard. The
82C606A and 82C606B devices are actually the same device with two
strapping options. Pulling the CONFI/2# pin high causes the device to
function in the 82C606A Mode. Pulling the CONFII2# pin low configures
the device to function in the 82C606B Mode of operation.
o 100-pin PQFP
o Mixed voltage to support 3.3V to 5.0V signal translation
o Two devices replace approximately eleven TTL devices
***Configurations:...
***Features:
o 100% PC/AT compatible
o Fully supports the 3.3V/5.0V Pentium processors
o Three chip solution:
- 82C547 System Controller (SYSC) (160-pin PQFP)
- 82C546 AT Bus Controller (ATC) (208-pin PQFP)
- 82C206 Integrated Peripheral Controller (IPC) (84-pin PLLC
or 100-pin PQFP)
o Two buffer/translator support chips:
- 82C606A (100-pin PQFP)
- 82C606B (100-pin PQFP)
o Supports Pentium CPU address pipelining
o 1X clock source, supporting systems running Pentium processor
bus clocks up to 60MHz
o Write-back, direct-mapped cache with size selections:
64KB, 128KB, 256KB, 512KB, 1MB and 2MB
o Programmable cache write policy: write-back or write-through
o Fully programmable cache and DRAM read/write cycles
o Supports 3-2-2-2 cache burst read cycles at 60MHz
o Built-in tag auto-invalidation circuitry
o Support for two programmable non-cacheable memory regions
o Options for cacheable, write-protected, system and video BIOS
o Supports two banks of 64-bit wide DRAMs with 256KB, 512KB, 1MB
2MB, 4MB and 8MBx36 Page Mode
o Supports DRAM configurations up to 128MB
o Supports 3-3-3-3 pipeline DRAM burst cycles
o DRAM post write buffer
o Support for flash ROM
o Shadow RAM option
o Hidden refresh with CAS-before-RAS refresh supported
o High-performance 32-bit local bus support
o Performance-oriented snoop-line comparator for VL/ISA
bus masters
o External DMA page register
o Turbo/slow speed selection
o Asynchronous CPU and VL bus interface
o AT bus clock speed programmability
o Transparent 8042 emulation for Fast CPU Reset and GATEA20
generation
o Supports Ports 92h, Gate A20, and Fast Reset
o Mixed voltage (3.3V and 5.0V), low-power, high speed, 0.8
micron CMOS technology
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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