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**440 series:
***440FX (Natoma)       05/06/96...
***440LX (Balboa)       08/27/97...
***440BX (Seattle)      c:Apr'98...
***440DX (?)            c:?...
***440EX (?)            c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?)          05/17/99...
***440MX (Banister)     05/17/99...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*Unresearched:...
*VIA...
**SLXXXX   Other chips
SL9091 Video Clock Chip
**
**VT82C470     "Jupiter", Chip Set (w/o cache) 386 [no datasheet]    ?
**VT82C475     "Jupiter", Chip Set (w/cache) 386   [no datasheet]    ?
**VT82C486/2/3 "GMC chipset"            [no datasheet, some info]    ?...
**VT82C495/480 "Venus" Chip Set                    [no datasheet]    ?
**VT82C495/491 ? EISA Chip Set          [no datasheet, some info]  <93...
**VT82C496G    Pluto, Green PC 80486 PCI/VL/ISA System       <05/30/94...
**VT82C530MV   3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M    Apollo Master, Green Pentium/P54C             <06/22/95...
**VT82C580VP   Apollo VP,  Pentium/M1/K5 PCI/ISA System      <02/15/96
***Info:...
***Configurations:...
***Features:
o   PCI/ISA Green PC Ready
o   High Integration
    - VT82C585VP system controller
    - VT82C586  PCI to ISA bridge
    - Two instances of the VT82C587VP data buffers
    - Six TTLs for a complete main board implementation
o   Flexible CPU Interface
    - 64-bit P54C, K5  and M1 CPU interface
    - CPU external bus speed up to 66Mhz (internal 200Mhz and above)
    - Supports CPU internal write-back cache
    - Concurrent CPU/cache and PCI/DRAM operation
    - System management interrupt, memory remap and STPCLK mechanism
    - Cyril M1 linear burst support
    - CPU NA#/Address pipeline capability
o   Advanced Cache Controller
    - Direct map write back or write through secondary cache
    - Burst Synchronous (Pipelined or non-pipelined), asynchronous 
      SRAM, and Cache Module support
    - Eight-pin CWE# and GWE# control options
    - Flexible cache size: 0K/256K/512K/1M/2MB
    - 32 byte line size to match the primary cache
    - Integrated 10-bit tag comparator
    - 3-1-1-1 read/write timing for Burst Synchronous SRAM access at 
      66Mhz
    - 3-1-1-1-1-1-1-1 back to back read timing for Burst Synchronous 
      SRAM access at 66Mhz
    - Sustained 3 cycle write access for Burst Synchronous SRAM access 
      or CPU to DRAM and PCI bus post write buffers at 66Mhz
    - 3-2-2-2 (read) and 4-2-2-2 (write) timing for interleaved 
      asynchronous SRAM access at 66Mhz
    - Data streaming for simultaneous primary and secondary cache line 
      fill
    - System and video BIOS cacheable and write-protect
    - Programmable cacheable region and cache timing
    - Optional combined tag and alter bit SRAM for write-back scheme
o   Fast DRAM Controller
    - Concurrent DRAM writeback
    - Four Cache lines (16 quadwords) of CPU/cache to DRAM write 
      buffers
    - Fast Page Mode/EDO/Burst EDO/Synchronous-DRAM support in a mixed 
      combination
    - Mixed 256K/512K/1M/2M/4M/8M/16MxN DRAMs
    - 6 banks up to 512MB DRAMs (maximum four banks of Synchronous 
      DRAM)
    - Flexible row and column addresses
    - 64 bit or 32 bit data width in arbitrary mixed combination
    - 3.3v and 5v DRAM without external transceivers
    - Speculative DRAM access
    - Read around Write capability for non-stalled CPU read
    - Burst read and write operation
    - 4-2-2-2 on page, 7-2-2-2 start page and 9-2-2-2 off page timing 
      for EDO DRAMs at 50/60Mhz
    - 4-2-2-2 on page, 8-2-2-2 start page and 11-2-2-2 off page timing 
      for EDO DRAMs at 66Mhz
    - 5-1-1-1 on page, 8-1-1-1 start page and 10-1-1-1 off page timing 
      for Burst EDO DRAMs at 66Mhz
    - 5-2-2-2-3-1-2-2 back-to-back  access for EDO DRAM at 66Mhz
    - 5-1-1-1-3-1-1-1 back-to-back  access for BEDO DRAM at 66Mhz
    - BIOS shadow at 16KB increment
    - System management memory remapping
    - Decoupled and burst DRAM refresh with staggered RAS timing
    - Programmable refresh rate, CAS-before-RAS refresh and refresh on 
      populated banks only
o   Unified Memory Architecture
    - Supports VESA UMA handshake protocol
    - Compatible with major video/GUI products
    - Direct video frame buffer access
    - Satisfies maximum latency requirement from REQ# to GNT# and from 
      GNT# to REQ#
o   Intelligent PCI Bus Controller
    - 32 bit PCI interface
    - Supports 66Mhz and 3.3v/5v PCI bus
    - PCI master snoop ahead and snoop filtering
    - PCI master Peer Concurrency
    - Synchronous Bus to CPU clock with divide-by-two from the CPU 
      clock
    - Automatic detection of data streaming burst cycles from CPU to 
      the PCI bus
    - Five levels (double-words) of CPU to PCI posted write buffers
    - Byte merging in the write buffers to reduce the number of PCI 
      cycles and to create further PCI bursting possibilities
    - Zero wait state PCI master and slave burst transfer rate
    - PCI to system memory data streaming up to 132Mbyte/sec
    - Sixty-four levels (double-words) of post write buffers from PCI 
      masters to DRAM
    - Thirty-two levels (double-words) of prefetch buffers from DRAM 
      for access by PCI masters
    - Enhanced PCI command optimization (MRL, MRM, MWI, etc)
    - Complete steerable PCI interrupts
    - Supports L1 write-back forward to PCI master read to minimize 
      PCI read latency
    - Supports L1 write-back merged with PCI master post-write to 
      minimize DRAM utilization
    - Provides transaction timer to fairly arbitrate between PCI 
      masters
    - PCI-2.1 compliant
o   Enhanced Master Mode PCI IDE Controller
    - Dual channel master mode PCI supporting four Enhanced IDE 
      devices
    - Transfer rate up to 22MB/sec to cover PIO mode 4 and Multiword 
      DMA mode 2 drivers and beyond
    - Sixteen levels (doublewords) of prefetch and write buffers
    - Interlaced commands between two channels
    - Bus master programming interface for ATA controllers SFF-8038 
      rev.1.0 compliant
    - Full scatter and gather capability
    - Support ATAPI compliant devices
    - Support PCI native and ATA compatibility modes
    - Complete software driver support
o   Universal Serial Bus Controller
    - USB v1.0 and Intel Universal HCI v1.0 compatible
    - Eighteen levels(doublwords) of data FIFOs
    - Root hub and two function parts with built-in physical layer 
      transceivers
    - Legacy keyboard and PS/2 mouse support
o   Plug and Play Controller
    - Dual interrupt and DMA signal steering with plug and play control
    - Microsoft Windows 95 and plug and play BIOS compliant
o   Sophisticated Power Management Unit
    - Normal, doze, sleep, suspend and conserve modes
    - System event monitoring with two event classes
    - One idle timer, one peripheral timer and one general purpose 
      timer
    - More than ten general purpose Input/Output ports
    - Six external event input ports with programmable SMI condition
    - Complete leakage control when external component is in power off 
      state
    - Primary and secondary interrupt differentiation for individual 
      channels
    - Clock stretching, clock throttling and clock stop control
    - Multiple internal and external SMI sources for flexible power 
      management models
    - Two programmable output ports
    - APM 1.1 compliant
o   PCI to ISA Bridge
    - Integrated 82C206 peripheral controller
    - Integrated keyboard controller with PS2 mouse supports
    - Integrated DS12885 style real time clock with extended 128 byte 
      CMOS RAM
    - Integrated USB (universal serial bus) controller with hub and 
      two function ports
    - Integrated master mode enhanced IDE controller with enhanced 
      PCI bus commands
    - PCI-2.1 compliant with delay transaction
    - Four double-word line buffer between PCI and ISA bus
    - Supports type F DMA transfers
    - Fast reset and Gate A20 operation
    - Edge trigger or level sensitive interrupt
    - Flash EPROM and combined BIOS support
o   Built-in nand-tree pin scan test capability
o   0.6um mixed voltage, high speed and low power CMOS process
o   208 pin PQFP for VT82C585VP
o   208 pin PQFP for VT82C586
o   100 pin PQFP for VT82C587VP

**VT82C580VPX  Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590     Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT  Apollo VP3, Single-Chip for Pentium with AGP  <10/03/97...
**VT82C598MVP  Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501       Apollo MVP4,Single-Chip 66-100MHz & AGP       <11/04/98...
**VT82C680     Apollo P6, Pentium-Pro Chip Set               <08/30/96...
**Support chips:
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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