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**82430FX     PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95
***Notes:...
***Info:
The 82430FX  PCIset consists of  the 82437FX System  Controller (TSC),
two 82438FX Data  Paths (TDP). and the 82371FB  PCI ISA IDE Xcelerator
(PIIX). The PCIset forms a  Host-to-PCI bridge and provides the second
level  cache control  and a  full function  64-bit data  path  to main
memory.  The  TSC integrates  the cache and  main memory  DRAM control
functions  and provides  bus control  for transfers  between  the CPU,
cache,  main memory, and  the PCI  Bus.  The  second level  (L2) cache
controller supports a  write-back cache policy for cache  sizes of 256
Kbytes and 512 Kbytes. Cacheless designs are also supported. The cache
memory can  be implemented with  either standard, burst,  or pipelined
burst SRAMs.  An  external Tag RAM is used for the  address tag and an
internal Tag  RAM for the cache  line status bits. For  the TSC’s DRAM
controller,  five rows  are supported  for up  to 128  Mbytes  of main
memory. The  TSC's Optimized PCI  interface allows the CPU  to sustain
the highest  possible bandwidth  to the graphics  frame buffer  at all
frequencies. Using the snoop ahead feature, the TSC allows PCI masters
to achieve full PCI bandwidth. The TDPs provide the data paths between
the   CPU/cache,  main   memory,  and   PCI.   For   increased  system
performance. the TDPs contain read prefetch and posted write buffers.


1.0 ARCHITECTURE OVERVIEW OF TSC/TDP
The 82430FX PCIset (Figure 1)  [see datasheet] consists of the 82437FX
System Controller (TSC).   two 82438FX Data Path (TDP)  units, and the
82371FB PCI  IDE ISA Xcelerator (PIIX).   The TS0 and two  TDPs form a
Host-to-PCI bridge. The PIIX  is a multi-function PCI device providing
a PCI-to-ISA bridge and a  fast IDE interface.  The PIIX also provides
power management and has a plug and play port.  The two TDPs provide a
64-bit data path  to the host and to main memory  and provide a 16-bit
data path  (PLINK) between  the TSC and  TDP. PLINK provides  the data
path for CPU to PCI accesses  and for PCI to main memory accesses. The
TSC and  TDP bus  interfaces are  designed for 3V  and 5V  busses. The
TSC/TDP connect  directly to  the Pentium processor  3V host  bus; The
TSC/TDP connect  directly to 5V or  3V main memory DRAMs;  and the TSC
connects directly to the 5V PCI Bus.

DRAM Interface
The DRAM interface  is a 64-bit data path  that supports both standard
page mode and Extended Data Out  (EDO) (also known as Hyper Page Mode)
memory. The DRAM  interface supports 4 Mbytes to  128 Mbytes with five
RAS  lines available  and also  supports symmetrical  and asymmetrical
addressing for 512K, 1M, 2M, and 4M deep DRAMs.

Second Level Cache
The  TSC supports a  write-back cache  policy providing  all necessary
snoop functions and inquire cycles.   The second level cache is direct
mapped and  supports both a 256-Kbyte or  512-Kbyte SRAM configuration
using  either burst, pipelined  burst, or  standard SRAMs.   The burst
256-Kbyte configuration performance  is 3-1-1-1 for read/write cycles;
pipelined back-to-back  reads can maintain  a 3-1-1-1-1-1-1-1 transfer
rate.

TDP
Two TDPs create a 64-bit CPU and main memory data path. The TDP's also
interface  to   the  TSC's  16-bit   PLINK  inter-chip  bus   for  PCI
transactions. The combination of the 64-bit memory path and the 16-bit
PLINK bus make the TDP’s  a cost effective solution, providing optimal
CPU-to-main  memory  performance  while  maintaining a  small  package
footprint (100 pins each).

PCI interface
The  PCI interface  is 2.0  compliant  and supports  up to  4 PCI  bus
masters in addition to the PIIX bus master requests. While the TSC and
TDP's together provide the interface between PCI and main memory, only
the TSC connects to the PCI Bus.

Buffers
The TSC and TDP's together contain buffers for optimizing data flow. A
four  Qword deep  butter is  provided for  CPU-to-main  memory writes,
second  level   cache  write  back  cycles,   and  PCI-to-main  memory
transfers. This  buffer is  used to achieve  3-1-1-1 posted  writes to
main memory.   A four Dword buffer  is used for  CPU-to-PCI writes. In
addition,  a four Dword  PCI Write  Buffer is  provided which  is com-
bined with the  DRAM Write Buffer to supply a  12 Dword deep buffering
for PCI to main memory writes.

System Clocking
The processor,  second level cache,  main memory subsystem,  and PLINK
bus  all  run synchronous  to  the host  clock.   The  PCI clock  runs
synchronously at half the host clock frequency. The TSC and TDP’s have
a host clock input and the TSC has a PCI clock input. These clocks are
derived from an external source and have a maximum clock skew require-
ment with respect to each other.

***Configurations:...
***Features:...
**82430MX     PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX     PCIset (Pentium) HX (Triton II) (82439HX)       02/12/96...
**82430VX     PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX     PCIset (Pentium) TX (Triton II) (82439TX)       02/17/97...
**82450KX/GX  PCIset (Pentium Pro) KX/GX (Mars/Orion)         11/01/95...
**
**Support Chips:
**82091AA     Advanced Interface Peripheral (AIP)                  c93...
**8289        Bus Arbiter (808x)                                   c79...
**82289       Bus Arbiter for iAPX 286 Processor Family            c83...
**82258       Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335       High-Integration Interface Device For 386SX      c:Nov88...
**82360SL     I/O Subsystem                                   10/05/90...
**82370       Integrated System Peripheral (for 82376)         c:Oct88...
**82371FB/SB  PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX     Mobile PCI I/O IDE Xcelerator (MPIIX)           11/01/95...
**82371AB     PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4)     02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB)   c:Mar93...
**82378       System I/O (SIO) (82378IB and 82378ZB)           c:Mar93...
**82379AB     System I/O-APIC (SIO.A)                           <Dec94...
**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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