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**Spelling errors/mistyped words
Yes, I  know there are  spelling errors,  and things are  mistyped. It
seems no matter  how hard I try  my fingers hit 't'  twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times.  I  don't have the  time or the will  to check the  spelling of
everything. Basic spell checking has been peformed. Please let me know
if  there is  anything that  would lead  to incorrect  information, or
something  is so  mangled  that  it needs  revising.  But  if you  can
basically  understand  what was  intended,  just  cope with  it.  Just
cope:-)

BTW, "110" port is  an "I/O" port that has been OCRed  badly, as is an
"1/0" port.

**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
**??????     "Bengal"  386DX/486 (WriteBack)     [no datasheet] cNov91
***Notes:...
***Configurations:...
**ET2000     386/486 WB Chipset                                      ?...
**ET6000     "Cheetah" 486DX/SX Non-Cache System                <Apr92...
**ET9000     "Jaguar" 486 Write Back Cache AT Single Chip       <Jun92
***Info:
The JAGUAR single chip provides high integration and low cost solution
for  a 16,  20, 25,  33  and 50MHz  486/AT based  system design.   Its
flexible architecture  allows Direct Mapped  Cache Implementation with
64KB/128KB/256KB/512KB  Cache.   The JAGUAR  combined  with 82C206  or
compatible peripheral controller offers a 100% PC/AT compatible system
using  less than  12 components  plus memory  devices.  The  ET9000 is
available in the 184-pin Plastic Quad Flatpack package.  The 1.0u high
speed, low power CMOS Technology allows for substantial stability when
running at 33 and 50MHz.

The JAGUAR  includes 486 CPU control,  write[back]-cache control, Page
Mode DRAM Control, a [local] DRAM control, AT Bus Control, Synchronous
AT Bus  Clock Generation, Clock  Switching Logic, data  bus conversion
logic which  performs the conversion  necessary between the 8,  16 and
32-bit  data paths.  A Coprocessor  Interface Logic  to  support Intel
487SX and Weitek 4167 are also included.

The  JAGUAR   ET9000  provides   very  flexible  cache   based  system
implementation  and a  Page Mode  DRAM memory  to  improve performance
during read  miss cycles.  System  performance is further  enhanced by
allowing  Refresh  and CPU  cache  hit  cycles  to occur  concurrently
without holding the CPU during Refresh cycle.

The system  cost is also minimized  by allowing the use  of slow SRAMs
and  DRAMs. The  "Write Back"  cache is  implemented to  minimize DRAM
access time during write cycle.

The JAGUAR is designed to be  100% compatible with the IBM PC/AT. With
its optimized Cache and DRAM design, enhanced features like Shadow RAM
BIOS, and  Concurrent Refresh; a high  performance / low  cost 486/ AT
can be implemented.

***Configurations:...
***Features:...
**ET9800/391 "Firefox" 386SX Write Back chipset [no datasheet]       ?...
**82C390SX   "Panda" S.C. 386SX Direct Mapped Cache [no d.sheet]cFeb92...
**66x8       VIA clones [no datasheet]                               ?...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...