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**M1217/M1209    386SX/SLC Single Chip (40MHz)    [no datasheet]   c91
***Notes:...
**M1219          386DX/486 ISA Cache? Single Chip [no datasheet]     ?
**M1419          386DX/486 ISA Cache  Single Chip [no datasheet]   c91
**Ml429/31/35    486 VLB/PCI/ISA      [no datasheet, some info] cOct93...
**M1439/31/45    486 VLB/PCI/ISA      [no datasheet, some info] <May95...
**M1489/87       FinALi-486 PCI Chipset                         <Feb95...
**M????          Genie, Quad Pentium  [no datasheet, some info]    c95...
**M1451/49       Aladdin    (Pentium) [no datasheet]                 ?...
**M1511/12/13    Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23       Aladdin III       50-66MHz                     <Nov96...
**M1531/33/43    Aladdin IV & IV+  50-83.3MHz                <05/28/97...
**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
**ET6000     "Cheetah" 486DX/SX Non-Cache System                <Apr92
***Info:
The  CHEETAH single  chip provides  high  integration and  a low  cost
solution  for  a  16,  20,  25,  33, and  50MHz  486/AT  based  system
design.  The CHEETAH  combined  with 82C206  or compatible  peripheral
controller offers  a 100% PC/AT  compatible system using less  than 10
components  plus  memory devices.  The  CHEETAH  is  available in  the
160-pin Plastic Quad Flat-pack package. The 1.0u high speed, low power
CMOS Technology  allows for substantial stability when  running at 25,
33, and 50MHz.

The CHEETAH includes  486 CPU control, AT Bus  Control, Page Mode DRAM
Control,  Asynchronous AT  Bus Clock  Generation, data  bus conversion
logic which performs the conversion necessary between the 8 and 16-bit
data paths, and Coprocessor Interface Logic to support Intel 487SX and
Weitek 4167.

The Cheetah  ET6000 is  a highly integrated  single chip  AT optimized
specifically for486 CPUs.  The emphasis of this chip  is to reduce the
cost   requirements   of   486  applications,   without   compromising
performance. Fast bursting can be achieved with 80ns DRAMs.

The  system  cost  is also  minimized  by  allowing  the use  of  slow
DRAMs. The  Burst Mode DRAM  control is implemented to  enhance system
performance.

The Cheetah is designed to be 100% compatible with the IBM PC/AT. With
its optimized Burst and DRAM design, enhanced features like Shadow RAM
BIOS, and  Concurrent Refresh; a high performance/low  cost 486/AT can
be implemented.

***Configurations:...
***Features:...
**ET9000     "Jaguar" 486 Write Back Cache AT Single Chip       <Jun92...
**ET9800/391 "Firefox" 386SX Write Back chipset [no datasheet]       ?...
**82C390SX   "Panda" S.C. 386SX Direct Mapped Cache [no d.sheet]cFeb92...
**66x8       VIA clones [no datasheet]                               ?...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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