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**82C593    3/486 [no datasheet]                                <May92
Listed in:
ftp://ami.com/archive/Other_Manuals/!index.txt
"
CTQ593_3.ZIP    74690   05-28-92  386   CONTAQ 82c593 CHIPSET  
CTQ593_4.ZIP    75792   05-28-92  486   CONTAQ 82c593 CHIPSET  
"
Note, the column of dates is the file date.





**82C596/A  3/486 Writeback Cache [no datasheet]             <11/11/92...
**??????    486 EISA chipset [no datasheet]                     <Feb93...
**82C599    PCI-VLB Bridge [no datasheet, some info]                 ?...
**82C693    PCI-ISA Bridge [no datasheet]                            ?...
*Efar Microsystems [no datasheets, some info]...
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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**UM82C206     Integrated Peripheral Controller                    <91
***Info:...
***Versions:...
***Features:
o   Fully compatible with PC/AT architecture
o   Fully compatible with 8237 DMA controller, 8259 Interrupt 
    controller, 8254 Timer/Counter, and 146818 Real Time Clock
o   Provides 7 DMA channels, 13 Interrupt request channels, 2 Timer/
    Counter channels, and a Real Time Clock
o   Built in 74LS612 memory mapper for DMA page address
o   Provides 114 bytes of CMOS RAM memory
o   8 MHz DMA clock with programmable internal divider for 4 MHz 
    operation
o   16M bytes DMA address space
o   Programmable wait states for the DMA cycle
o   Reduced recovery time (120 ns) between I/O operations 



**UM82c45x     Serial/Parallel chips                                 ?...
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