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**F87000 Multi-Mode Peripheral Chip 11/23/93
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**Disk:
82C5058 Single chip SCSI Disk Controller 10MB/s
82C5059 Single chip PC-AT Disk Controller 20MHz ESDI
82C765 Floppy Disk Controller (1Mb/s)
82C785 Single chip PC-AT Hard Disk Controller (Conners Interface!?>>?IDE?)
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*Contaq . . . . . [no datasheets, some info]...
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**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
**HTK320 386DX Chip Set c:Sep91
***Info:
The HTK320 chip set is a 2-chip, high-performance, cost-effective
solution for the 80386DX microprocessor. In its minimum configuration,
this highly integrated chip set requires only four external TTL
devices to implement a fully compatible IBM PC/AT system at speeds up
to 40 MHz.
The HTK320 is based on Headland’s Bus Architecture and consists of the
HT321-ISA Controller and the HT322-Memory Control Unit (MCU) packaged
in two 184-pin plastic quad flat packs. Among its features are an
on-chip cache controller and internal tag RAM.
Unlike other 3rd generation chip sets that have integral Cache
Controllers, the HTK320 integrates the high-speed tag RAM into the
chip set to enhance performance and significantly reduce component
count and manufacturing cost. The direct mapped or 2-way set
associative cache design supports external cache sizes of 32K, 64K,
and 128K.
The HTK320 can support Peripheral Devices such as VGA or SCSI
controllers on the local processor bus, or any 3rd party device that
is designed to work within the 386DX Bus Protocol and Timing. By
eliminating the ISA backplane bottleneck, system designers can greatly
improve the performance of functions such as graphics generation and
disk access.
The HTK320 incorporates a 4-leve1 deep Write Buffer and performs byte
gathering into 32 bit accesses to the DRAM. This facilitates real
zero wait state writes and, when coupled with the 2-way set
associative cache, provides enhanced memory performance.
The HTK320 Supports up to 4 banks of DRAM, configurable as 1-4 Banks.
This flexible memory architecture allows for any memory type, from
256Kb to 16Mb devices, in any bank. Maximum system performance is
achieved from the DRAM banks through various means, including
interleave of Memory Bank and/or Page, and CAS before RAS refresh.
The memory may also be tuned to its maximum potential through the use
of extensive DRAM timing Control Registers, controls include,
Precharge time, Access time on Reads, Active time on Writes, as well
as CAS and RAS delays. In addition, further system performance is
gained by separate timing parameters on the read and Write cycles
which allow system designers to take maximum advantage of the
pipelined structure of the chip set.
The HTK320 also supports extensive mapping registers, which allow
system designers to take maximum advantage of system memory. The chip
set supports EMS LIM 4.0, allows for mixed Shadow/Remap in 16K blocks
between the 640K and 1M boundaries, and eliminates the requirement fer
external decoding logic by support of 27 Programmable Non-cache
regions. With the' extensive HTK320 mapping capability, it is
feasible to seamlessly place 3rd party devices on the local bus
without the need for external TTL support. The HTK320 Mapping
structure provides for a single 8-bit EPROM to be used for both the
system and Video BIOS, further reducing the system chip count and
cost.
***Configurations:...
***Features:...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
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