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**Spelling errors/mistyped words
Yes, I  know there are  spelling errors,  and things are  mistyped. It
seems no matter  how hard I try  my fingers hit 't'  twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times.  I  don't have the  time or the will  to check the  spelling of
everything. Basic spell checking has been peformed. Please let me know
if  there is  anything that  would lead  to incorrect  information, or
something  is so  mangled  that  it needs  revising.  But  if you  can
basically  understand  what was  intended,  just  cope with  it.  Just
cope:-)

BTW, "110" port is  an "I/O" port that has been OCRed  badly, as is an
"1/0" port.

**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**82C721   Universal Peripheral Controller III                 c:May93
***Info:...
***Versions:...
***Features:...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91
***Info:
The 82C835 interfaces directly with the 386sx and has been designed to
work  closely with  the 82C836  single chip  AT (SCAT-sx).  The 82C835
contains  a 386sx  cache  controller incorporating  the cache  control
logic and  tag RAM.  Also included are  several programmable registers
provided for configuration options. The ability to configure the cache
organization (Two-Way Set-Associative or Direct Mapped) and size (16KB
or 32KB) allows a flexible selection of external data SRAM.

In addition to the cache  controller, the 82C835 integrates the AT I/O
channel  command and  address  buffers and  the corresponding  control
logic. Many existing 80386sx system implementations require the use of
external buffers,  latches, and transceivers to drive  and receive the
commands and addresses.  These systems also require external SSI logic
to control the operation of these buffers. Systems will typically save
six  to seven  external TTL  buffers and  five to  six SSI  gates when
implementing the channel interface with the 82C835. By integrating the
channel  drivers and  logic, the  82C835 reduces  the system  size and
complexity.

***Versions:...
***Features:...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...