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**M1217/M1209    386SX/SLC Single Chip (40MHz)    [no datasheet]   c91
***Notes:...
**M1219          386DX/486 ISA Cache? Single Chip [no datasheet]     ?
**M1419          386DX/486 ISA Cache  Single Chip [no datasheet]   c91
**Ml429/31/35    486 VLB/PCI/ISA      [no datasheet, some info] cOct93...
**M1439/31/45    486 VLB/PCI/ISA      [no datasheet, some info] <May95...
**M1489/87       FinALi-486 PCI Chipset                         <Feb95...
**M????          Genie, Quad Pentium  [no datasheet, some info]    c95...
**M1451/49       Aladdin    (Pentium) [no datasheet]                 ?...
**M1511/12/13    Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23       Aladdin III       50-66MHz                     <Nov96...
**M1531/33/43    Aladdin IV & IV+  50-83.3MHz                <05/28/97...
**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**82C721   Universal Peripheral Controller III                 c:May93
***Info:
The CHIPS  82C721 enhanced I/O peripheral controller  is a single-chip
solution  offering  complete  I/O  capabilities for  PC/AT  and  PC/XT
environments.  The  82C721   supports  motherboard  applications  with
configuration via software.

The  82C721  features  a   floppy  disk  controller,  a  digital  data
separator, two 16450 compatible UARTs, a bi-directional parallel port,
an IDE interface control logic and a game port chip select.

The floppy  disk controller is software compatible  with NEC uPD72065B
floppy  disk controller.  The  controller supports  up to  four drives
directly. The digital data separator is capable of data transfer rates
up to 500kb/sec and requires no external components.

The 82C721 has two UARTs  which are compatible with NS16450 UARTs. The
IDE control logic provides a  complete IDE interface for embedded hard
disk  drives.  The  bidirectional  parallel  port  maintains  complete
compatibility with ISA and PS/2  parallel ports.  It can be configured
for either output mode or for bidirectional mode.

The  configuration   RAM  and  circuitry   support  programmable  base
addresses for  all the registers. Selection of  sources of interrupts,
enabling and configuring of on-chip  subsystems and the control of the
configuration  process itself  are also  handled by  this RAM  and its
associated circuitry.  The game port chip select provides a predefined
I/O address decode for games and joy stick applications.

The 82C721,  designed for  motherboard applications, is  provided with
several  power  management features,  which  are controllable  through
hardware  or  software. In  hardware,  the  device  can be  completely
powered down through  a power-down pin.  In this  mode, all inputs are
disabled, all outputs are inactive,  and the contents of all registers
are  preserved  (as long  as  the  power  supply is  maintained).   In
software,   the  device   allows  each   port  to   be   powered  down
independently.

The  82C721 features 24mA  drivers for  output buffers,  including the
host  data bus  and  the parallel  port  data bus.  The floppy  output
drivers  are  capable  of  sinking  48mA. The  host  interface  is  PC
compatible and can be connected directly to the ISA bus.

***Versions:...
***Features:...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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