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**64200 (Wingine) High Performance 'Windows Engine' c:Oct91
***Info:
****General:
The concept behind the 64200 'Windows Engine' (Wingine) is the
implementation of video display memory as a bank (or banks) of system
memory. The idea is that the system CPU (typically at least a
386-class processor) can manipulate pixels on the screen quickly if
the display memory bottleneck is removed. The video memory is
accessed directly by the system CPU as a frame buffer through the VRAM
random access port while the display is continuously being refreshed
via the VRAM serial data port.
Wingine is basically a standard 16-bit VGA with extensions. The
primary extension is to allow the system to directly access VRAM
display memory as system memory. Wingine operates in two modes:
'Windows Acceleration' mode and 'VGA' mode. In 'VGA' mode, Wingine
drives the video memory. Wingine uses the VRAMs as DRAMs in VGA mode
(no special capabilities of the VRAMs are required or used); all VGA
operations are implemented via the VRAM random access port. (Wingine
pinouts are defined such that future implementations may be extended
to take advantage of the VRAM serial port in VGA mode.) In 'Windows
Acceleration' mode, the VRAM random access ports are driven by the
system memory controller; the Wingine chip does not have access to the
VRAMs, but performs all VRAM serial data shift operations and provides
HSYNC and VSYNC for the display monitor. In 'Windows Acceleration'
mode, the system performs all data transfer operations based on
information provided from the Wingine chip.
The result is very high performance, since the entire random port
bandwidth is available for CPU access and the VRAMs may always be
accessed at full memory speed. In addition, memory may be accessed at
the full width of system memory (16 or 32 bits). The frame buffer may
be accessed as a linear array of pixels (in 'packed- pixel' format)
anywhere in the system memory space.
Another major advantage is the ability to accept 32 bits of serial
data from the VRAMs and convert it into an 8-bit video data stream
compatible with a standard low-cost VGA RAMDAC. This capability
removes the requirement for an expensive RAMDAC, allowing
implementation of cost effective, high performance graphics system.
Wingine directly supports 4bpp (nibble) and 8bpp (byte) modes with
standard VGA 8-bit RAMDACs which are available up to 80 MHz. 16bpp
mode may be supported with an extended capability RAMDAC such as a
Sierra SC11482, 483, or 484. Wingine can also support various types of
high performance and extended capability RAMDACs with 32-bit parallel
data input ports. These RAMDACs typically support pixel rates to 135
MHz and modes of 1bpp, 2bpp, 4bpp, 8bpp, 16bpp, and / or 24bpp. All
known RAMDACs support these modes lsb first (e.g., nibble modes shift
the first pixel out of bits 0-3 of the first byte in memory, the
second pixel out of bits 4-7, etc). All of these modes up to 16bpp
are also supported in the XGA ('lsb first' is referred to as 'Intel
order' in IBM's XGA documentation). Therefore, for compatibility,
pixel shift order is always lsb first and pixels are always stored in
Wingine memory as a linear array of n-sized elements starting with
bit-0 of byte 0.
DISPLAY MEMORY CONFIGURATIONS
The VRAM frame buffer may be implemented with two, four, or eight
256Kx4 (1Mb) or two or four 256Kx8 (2Mb) VRAMs, accessed as 1 bank of
32-bit memory in 386 DX or 486 systems or as 2 banks of 16-bit memory
in 386 SX systems. This provides 1MB of display memory, which is
adequate for support of 1024x768 at 8bpp (256-color). This amount of
memory, using split buffer VRAMs and a Sierra RAMDAC (or equivalent),
will also support 16bpp modes up to 800x600.
Wingine allows 512KB upgradable to 1MB of display memory in 386 SX
(16-bit) systems by optionally populating the upper bank. The 512KB
configuration supports 1024x768 at 4bpp (16-color) and 640x480 at 8bpp
(256-color). If word interleaving is done in 16-bit systems, the
memory map is identical between 16 and 32 bit systems (and the same
drivers may be used). Wingine is designed to also handle
non-word-interleaved 2 bank 16-bit memory maps, if word interleaving
is not implemented by the system.
If 256Kx4 VRAMs are used, 512KB of display memory (upgradable to 1MB)
may also be implemented by optionally populating the upper nibble of
each byte. In this configuration, the system would always manipulate
display memory assuming 8bpp; screen display would be 16-color with 4
VRAMs installed and 256-color with 8 VRAMs installed (the RAMDAC pixel
mask register would be set to mask out the upper 4 bits of video data
in 4-VRAM mode).
Wingine will support 24bpp modes up to 640x480 in 1MB configurations,
but a RAMDAC must be used which allows packing R, G, & B every 3 bytes
and AT&T 206491 RAMDACs. The Bt482 support this type of pixel
packing. However Wingine will support 24bpp modes up to 640x400 if the
RAMDAC ignores one byte out of every four. Many 32-bit input RAMDACs
(Bt484 / 485, TI 34075 / 34076) support 24bpp mode in this fashion (by
ignoring the upper byte of the 32-bit input). Since only one pixel is
input to the RAMDAC every shift clock, the maximum pixel rate in this
mode is limited by the VRAM shift clock rate: 33 MHz for '-10' (100ns)
VRAMs and 40 MHz for '-8' (80ns) VRAMs).
Wingine supports interlaced displays at 1024x768 resolution. Wingine
maintains a linear address mapping scheme so that software drivers are
independent of whether the display is interlaced or not.
Wingine is compatible with VRAM memory configurations larger than 1MB,
if implemented by the system as either multiple banks of 32-bit memory
using '256K x N' VRAMs or single banks of 32-bit memory using '512K x
N' or '1M x N' VRAMs. These configurations would typically be
implemented with 32-bit input extended-function, high-performance
RAMDACs and support high resolutions (e.g., 1280x1024) and/or
high-color modes (16bpp and 24bpp).
SYSTEM SUPPORT REQUIREMENTS
To implement a Wingine-based Graphics sub-system, the system memory
controller must be able to map a bank (or banks) of VRAMs into the
system memory space. The memory controller must be aware of the
differences between VRAMs and DRAMs for random access port control
(the VRAM serial port is controlled by Wingine). Wingine support
exists in the CS4021 486 CHIPSet. Chips and Technologies plans to
provide Wingine support in all future Systems Logic CHIPSets and
SYSTEMSets to allow Wingine to interface directly to those products.
Extensions are also planned for all current CHIPSets and SYSTEMSets.
MEMORY INTERFACE
Two types of memory subsystems can be designed with Wingine. In the
first type, 2 or 4 DRAMs can be used for VGA compatible modes. For
Wingine modes, separate VRAMs are used. In this implementation, VGA
memory and 'Wingine mode' memory are separate. No external buffers
are required to isolate the two memory buses.
In the second type of memory subsystem, a shared memory bus is used
for a cost effective implementation. In this case, only VRAMs are
used. In VGA mode, Wingine controls video memory. In 'Wingine' mode,
the system memory controller has control over video memory. External
buffers are required to isolate the two buses - the Wingine memory bus
and the system memory bus. Refer to the following section for
additional details.
Wingine can support up to 2 Mbytes of display memory. It can also
support 256 Kbyte and 512 Kbyte memory configurations. The following
table shows a matrix of resolution and memory requirements. This
table assumes a shared memory architecture. It is important to
buffers SCLK with a fast buffer when 2 Mbyte configuration is used.
Resolution Memory
VGA Mode 640x480 16 Colors 256 Kbytes
800x600 16 Colors 256 Kbytes
640x480 256 Colors 512 Kbytes
1024x768 16 Colors 512 Kbytes
Wingine Mode 640x480 256 Colors 512 Kbytes
800x600 256 Colors 512 Kbytes
1024x768 256 Colors 1 Mbyte
640x480 16 bits/pixel 1 Mbyte
640x480 24 bits/pixel 1 Mbyte
800x600 16 bits/pixel 1 Mbyte *
1024x768 16 bits/pixel 2 Mbyte**
1280x1024 256 colors 2 Mbytes
>* Requires Split - Buffer VRAMs.
>** Requires Bt484 compatible DAC.
RECOMMENDED MEMORY CHIPS
Standard Split Buffer
Micron MT42C4256
Mitsubishi 442256
Toshiba 524256
NEC 42273
SYSTEM INTERFACE
The 64200 Wingine chip is tightly coupled to system chipsets from
Chips and Technologies. This tight coupling between Wingine and the
system chipset results in a very high performance Windows
architecture. The Wingine graphics controller can be interfaced to
two high performance CHIPSets from Chips & Technologies - the CS4021
and CS82310 chipsets.
****Wingine/CS4021 Interface:...
****Wingine/CS82310 Interface:...
****More:...
***Versions:...
***Features:...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
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*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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