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**82C836   Single Chip 386sx (SCATsx)                              <91
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**F8680/A  PC/CHIP Single-Chip PC                                  c93...
**
**Support Chips:
**64200    (Wingine) High Performance 'Windows Engine'         c:Oct91...
**82C206   Integrated Peripheral Controller                        c86...
**82C601/A Single Chip Peripheral Controller                 <08/30/90...
**82C607   Multifunction Controller                             <Jun88...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



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**82C802G/GP     System/Power Management Controller (cached)      c:93
***Notes:...
***Info:...
***Configurations:...
***Features:
[features found only in the 802GP are marked in [] brackets ]

o   Processor interface:
    - Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D
    - AMD 486SX, DX2, DXL, DXL2, Plus
    - Cyrix DX, DX2, M7
    - CPU frequencies supported 20, 25, 33, 40 and 50MHz
o   Cache interface:
    - Direct mapped cache
    - Two banks interleaved or single bank non-interleaved
    - 64, 128, 256 and 512K cache sizes
    - Programmable wait states for L2 cache reads and writes
    - 2-1-1-1 read burst and zero wait state write @ 33MHz
    - No Valid bit required
   [- Supports external single-chip cache modules from thyroid-party ]
   [  vendors for high performance at 50MHz                          ]
    - Supports CPUs with L1 write-back support
o   DRAM interface:
    - Up to 128MB main memory support
    - Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM 
      modules
    - Read page hit timing of 3-2-2-2 at 33MHz
    - Supports hidden, slow. and CAS-before-RAS refresh
    - Four RAS lines to support four banks of DRAM
   [- Eight RAS lines to support four banks of DRAM  ]
    - Programmable wait states for DRAM reads and writes
   [- Programmable memory holes for supporting ISA memory ]
    - Enhanced DRAM configuration map
   [- Strong drivers on the MA lines (12/24mA) ]
   [- Supports asymmetric DRAMs                ]
o   Power management:
    - Support for SMM (System Management Mode) for system power 
      management implementations
    - Programmable power management
   [- CPU clock control ]
    - Programmable wake-up events through hardware, software, and 
      external SMI source
    - Multiple level GREEN support (NESTED_GREEN)
    - STPCLK# protocol support
   [- Programmable GREEN event timer       ](802G  only)
   [- Individually programmable peripheral ](802GP only)
o   ISA interface:
    - 100% IBM PC/AT ISA compatible
   [- Programmable edge- or level-trigger interrupts ]
    - integrates DMA, timer and interrupt controllers
   [- Slew rate control for output drivers           ]
    - Optional PS/2 style IRQ1 and IRQ12 latching
o   VESA VL interface:
    - Conforms to the VESA V2.0 specification
    - Optional support for up to two VL masters
o   Miscellaneous features:                              (802G only)
    - Full support for shadow RAM, write protection, L1/L2 
      cacheability for video, adapter, and system BIOS
    - Enhanced arbitration scheme
    - Transparent 8042 emulation for fast CPU reset and GATEA20 
      generation
o  [Miscellaneous features:                             ](802GP only)
   [- Full support for flash, write protection, L1/L2   ]
   [  cacheability for video, adapter, and system BIOS  ]
   [- Provides Micro Channel bridge support             ]
   [- 10-/16-nit I/O decodes                            ]
   [- Enhanced arbitration scheme                       ]
o   Packaging:
    - Higher integration
    - Reduced TTL count
    - Low-power, high~speed 0.8-micron CMOS technology
    - 208-pin PQFP (Plastic Quad Flat Pack)

**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
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