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**M1521/23       Aladdin III       50-66MHz                     <Nov96
***Info:...
***Configurations:...
***Features:...
**M1531/33/43    Aladdin IV & IV+  50-83.3MHz                <05/28/97...
**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**CS8231   TURBO CACHE-BASED 386/AT (82C301/307/303/304/305/306)   c86
***Info:
The  CS8231 TURBO  CACHE BASED  386/AT CHIPSet  is a  seven  chip VLSI
implementation of most of the  system logic to implement a CACHE BASED
iAPX 386 based system.  The CHIPSet  is designed to offer a 100% PC AT
compatible  integrated  solution.  The  flexible  architecture of  the
CHIPSet allows it to be used  in any iAPX386 based system design, such
as  CAD/CAE  workstations, office  systems,  industrial and  financial
transaction systems.

The CS8231 CHIPSet combined with CHIP's 82C206, Integrated Peripherals
Controller, provides a complete PC  AT compatible system using only 40
components  plus memory devices.  

The CS8231 CHIPSet  consists of one 82C301 Bus  Controller, one 82C307
Integrated  CACHE/DRAM  controller,  one  each of  82A303  and  82A304
Address Bus Interfaces,  two 82B305 Data Bus Interfaces,  and a 82A306
Control Signal Buffer.

The CHIPSet supports a local CPU  bus, a 32-bit system memory bus, and
AT buses as  shown in the system diagram below.  The 82C301 and 82A306
provide the generation and  synchronization of control signals for all
buses.  The 82C301  also supports  an  independent AT  bus clock,  and
allows for  dynamic selection of  the processor clock between  the 16M
Hz, 20MHz, or  25MHz clocks and the AT bus  clock. The 82A306 provides
buffers  for bus control  signals in  addition to  other miscellaneous
logic functions.

The  82C307 is  a  high performance  and  high integration  CACHE/DRAM
controller  designed  to  interface   directly  to  the  80386  micro-
processor.   It maintains frequently  accessed code  and data  in high
speed memory, allowing the 80386 to operate at its maximum rated freq-
uency with  near zero waitstates.   By integrating DRAM  control func-
tions on-chip,  it supports simultaneous activation of  cache and DRAM
access,  thereby  minimizing the  cache  miss  cycle  penalty. It  has
hardware support to allow the user  to designate up to four blocks (of
variable  size from  2KB to  128KB)  of main  memory as  non-cacheable
address  space.  This  feature is  important for  compatibility issues
when operating in a multiprocessing or LAN environment, or where dual-
port memory is used, and to  designate certain regions of video RAM as
non-cacheable. This feature eliminates the  need to use very fast PALs
externally  to decode non-cacheable  regions and  gives the  user much
more flexibility. Optional  EDC support logic is integrated  on to the
82C307  which  allows  it  to  interface to  any  of  the  generically
available 32-bit Error Detection  and Correction Circuits to realize a
highly reliable memory subsystem.

Cache coherency is maintained during DMA cycles by channeling all acc-
esses through the cache controller logic.  During DMA read operations,
the cache  RAM is  not accessed  and data is  retrieved from  the main
memory.  During DMA write operations,  if a cache hit is detected, the
cache  RAM is  updated  and the  corresponding  tag validated.   Cache
coherency  is maintained at  all times,  with no  performance penalty.
The  82C307 is  available in  a 100  pin PFP  package. 

The 82A303  and 32A304  interface between all  address buses,  and the
addresses needed for proper data path conversion.  Two 828305 are used
to interface between the local,  system memory, and at data buses.  In
addition  to  having  high   current  drive,  they  also  perform  the
conversion necessary between the different sized data paths.

***Configurations:...
***Features:...
**CS8232   CMOS 386/AT              (82C301/302/303/304/305/306)   c86...
**CS8233   PEAK/386 AT (Cached)     (82C311/82C315/82C316)     c:Dec90...
**CS8236   386/AT                   (82C301/2/3/4/5/6/206)         c86
***Notes:...
**CS8237   TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206)         c86...
**CS8238   CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226)   c:Aug89...
**CS82310  PEAK/DM 386 AT           (82C351/82C355/82C356)         c91...
**CS8281   NEATsx (386SX)           (82C811/812/215/206)       c:Dec89...
**CS8283   LeAPset-sx               (82C841/82C242/82C636)     c:Mar90...
**CS8285   PEAKsx                   (82C836/82C835)                c91...
**CS8288   CHIPSlite-sx             (82C836/82C641/82C835)          c?...
**CS4000   WinCHIPS                 (64200/84021/84025)            c92...
**CS4021   ISA/486                  (84021/84025)                  c92...
**CS4031   CHIPSet                  (84031/84035)              5/10/93...
**CS4041/5 CHIPSet                  (84041/84045)              2/10/95...
**CB8291   ELEAT                    [no datasheet]                 c90...
**CB8295   ELEATsx                  [no datasheet]                 c90...
**82C100   IBM PS/2 Model 30/Super XT                                ?...
**82C110   IBM PS/2 Model 30/Super XT                                ?...
**82C235   Single Chip AT (SCAT)                                   c89...
**82C836   Single Chip 386sx (SCATsx)                              <91...
**F8680/A  PC/CHIP Single-Chip PC                                  c93...
**
**Support Chips:
**64200    (Wingine) High Performance 'Windows Engine'         c:Oct91...
**82C206   Integrated Peripheral Controller                        c86...
**82C601/A Single Chip Peripheral Controller                 <08/30/90...
**82C607   Multifunction Controller                             <Jun88...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



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