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**Spelling errors/mistyped words
Yes, I  know there are  spelling errors,  and things are  mistyped. It
seems no matter  how hard I try  my fingers hit 't'  twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times.  I  don't have the  time or the will  to check the  spelling of
everything. Basic spell checking has been peformed. Please let me know
if  there is  anything that  would lead  to incorrect  information, or
something  is so  mangled  that  it needs  revising.  But  if you  can
basically  understand  what was  intended,  just  cope with  it.  Just
cope:-)

BTW, "110" port is  an "I/O" port that has been OCRed  badly, as is an
"1/0" port.

**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
**W860551/P UART with FIFO and Printer Port Controller             <94
***Info:...
***Versions:...
***Features:
o  Easily interfaces with most popular microprocessors
o  Pin compatible and functionally compatible with the existing 
   W860451
o  Centronics parallel interface
o  Capable of running all existing 16450 and 16550 software
o  Uses system's 14.3181 BMHz clock input
o  In FIFO mode transmitter and receiver are each buffered with 
   16-byte FIFOs to reduce number of intercepts presented to the CPU
o  Adds or deletes standard asynchronous communication bits (start, 
   stop, and parity) to or from serial data
o  Independently controlled transmit, receive, line status, and data 
   set interrupts
o  Programmable baud rate generator
o  Modem control functions (CTS, RTS, DSR, DTR, RI, and DCD)
o  Fully programmable serial-interface characteristics:
   - 5, 6, 7, or 8-bit characters
   - Even, odd, or no-parity bit generation and detection
   - 1, 1.5, or 2-stop bit generation
   - Baud generation
o  False start bit detection
o  Internal diagnostic capabilities:
   - Loopback controls for communications link fault isolation
   - Break, parity, overrun, framing error simulation
o  Fully prioritized interrupt system controls
o  40-pin PDIP package for W860551 and 44-pin PLCC package for 
   W86C551P

**
**Other:...
*ZyMOS...
*General Sources:...