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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



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**UM82C852     Multi I/O For XT                                    <91
***Info:...
***Versions:...
***Features:
o   Supports game port
o   Supports 2nd serial port
o   Centronics printer interface
o   Independent control of transmit, receive, line status and data set 
    interrupts
o   Individual modem control signals
o   Programmable serial interface characteristics:
    — 5, 6, 7 , or 8 bit characters
    — Even, odd or no-parity bit generation and detection
    — 1, 1-1/2, or 2 stop bit generation
o   Milliseconds through month counters for real time clock 56 bits of
    RAM 
    with comparator for comparing the real time counter to the RAM 
    data
o   POWER DOWN input that disables all inputs and outputs
o   Disables the chip from the reset of the system for standby low 
    power operation by use of a POWER DOWN input
o   32,768 Hz crystal for real time clock
o   Four-year calendar (no leap year)
o   24-hour clock

**UM82C206     Integrated Peripheral Controller                    <91...
**UM82c45x     Serial/Parallel chips                                 ?...
**Other chips:...
*Unresearched:...
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*Winbond...
**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89
***Info:
GENERAL DESCRIPTION

The W860451 is an enhanced version of the popular W860450 asynchronous
communication element  (ACE) fabricated using  WINBOND'S CMOS process.
The  device   supports  one  serial-to-parallel   conversion  on  data
characters  received  from  a  peripheral  device  or  a  MODEM.   and
parallel-to-serial  conversion on  data characters  received  from the
CPU. The  CPU can  read the complete  status of  the UART at  any time
during the functional  operation. Status information reported includes
the type and  condition of the transfer operations  being performed by
the UART as well as any error conditions (parity, overrun, framing. or
break  interrupt).   The  UART   includes  a  programmable  baud  rate
generator that is capable of dividing the timing reference clock input
by divisors of 1 to (2^16 -  1), and producing a 16x clock for driving
the internal  transmitter logic. Provisions  are also included  to use
this  16x clock  to drive  the receiver  logic.  The  UART  includes a
complete  MODEM-control capability  and a  processor-interrupt system.
interrupts can  be programmed  to the user’s  requirements, minimizing
the computing required to handle the communications link.  In addition
to its communication interface  capabilities, the W860451 provides the
user with a parallel Centronics type printer.
***Versions:...
***Features:...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
*General Sources:...