[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
**Spelling errors/mistyped words
Yes, I know there are spelling errors, and things are mistyped. It
seems no matter how hard I try my fingers hit 't' twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times. I don't have the time or the will to check the spelling of
everything. Basic spell checking has been peformed. Please let me know
if there is anything that would lead to incorrect information, or
something is so mangled that it needs revising. But if you can
basically understand what was intended, just cope with it. Just
cope:-)
BTW, "110" port is an "I/O" port that has been OCRed badly, as is an
"1/0" port.
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89
***Info:...
***Versions:...
***Features:
o Easily interfaces to most popular microprocessors.
o Adds or deletes standard asynchronous communication bit (start,
stop, and parity) to or from serial data stream.
o Holding and shift registers eliminate the need for precise
synchronization between the CPU and the serial data.
o Independently controlled transmit, receive, line status, and data
set interrupts.
o Programmable baud generator allow division of any input clock by 1
to (2^16 - 1) and generates the internal 16x clock.
o Independent receiver clock input.
o MODEM control functions (CTS, RTS. DSR, DTR, RI, and DCD).
o Fully programmable serial-interface characteristics:
- 5, 6, 7, or 8-bit characters
- Even, odd, or no-parity bit generation and detection
- l, 1.5 or 2-stop bit generation.
- Baud generation (DC to 56K baud).
o False start bit detection.
o Complete status reporting capabilities.
o TRl-STATE TTL drive capabilities for bidirectional data bus and
control bus.
o Line break generation and detection.
o Internal diagnostic capabilities:
- Loopback controls for communications link fault isolation.
- Break, parity, overrun, framing error simulation.
o Fully prioritized interrupt system controls.
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
**Other:...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved