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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



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**UM82C852     Multi I/O For XT                                    <91
***Info:...
***Versions:...
***Features:
o   Supports game port
o   Supports 2nd serial port
o   Centronics printer interface
o   Independent control of transmit, receive, line status and data set 
    interrupts
o   Individual modem control signals
o   Programmable serial interface characteristics:
    — 5, 6, 7 , or 8 bit characters
    — Even, odd or no-parity bit generation and detection
    — 1, 1-1/2, or 2 stop bit generation
o   Milliseconds through month counters for real time clock 56 bits of
    RAM 
    with comparator for comparing the real time counter to the RAM 
    data
o   POWER DOWN input that disables all inputs and outputs
o   Disables the chip from the reset of the system for standby low 
    power operation by use of a POWER DOWN input
o   32,768 Hz crystal for real time clock
o   Four-year calendar (no leap year)
o   24-hour clock

**UM82C206     Integrated Peripheral Controller                    <91...
**UM82c45x     Serial/Parallel chips                                 ?...
**Other chips:...
*Unresearched:...
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*Winbond...
**W83769          Local Bus IDE Solution                           <94
***Info:
GENERAL DESCRIPTION

The W83769  is a  high-performance, low-cost, highly  integrated logic
design  for IDE hard  disk applications  in PCI  (Peripheral Component
Interconnect)  local  bus systems.  It  provides  a  bridge between  a
standard  IDE  drive  and the  PCI  local  bus.  The W83769  is  fully
compatible  with the  ANSI ATA  3.0 specifications  for IDE  hard disk
operation  and the  PCI SIG  revision 2.0  specifications for  the PCI
local bus  protocol. Packaged in  a 100-pin PQFP, the  W83769 directly
supports the 32-bit PCI bus without requiring any external TTLs.

The W83769  operates at up to 50  MHz and provides a  full 32-bit data
path to the PCI bus. Doubleword read and write operations are provided
via  internal   control  and  conversion  logic.   Write  posting  and
read-ahead  allows CPU  memory  cycles to  run  concurrently with  IDE
cycles and improves the hard disk buffer-to-host transfer rate.

The IDE  drive interface timing  of the W83769 is  completely software
programmable,  including command  active/recovery  timing and  address
setup-hold   timing  for   each  drive.   The  device   supports  Fast
ATA/Enhanced  IDE  mode  3  timing  and IORDY  monitoring  for  better
performance.   The  W83769  directly  supports four  IDE  drives  with
170/1F0   dual   IDE  connectors.   The  IO base   addresses  of   the
primary/secondary  IDE connector  are exchangeable  by  power-on strap
option.

***Versions:...
***Features:...
**
**UARTS:
**W86C250A  UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter         <Jul89...
**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
*General Sources:...