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**Spelling errors/mistyped words
Yes, I  know there are  spelling errors,  and things are  mistyped. It
seems no matter  how hard I try  my fingers hit 't'  twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times.  I  don't have the  time or the will  to check the  spelling of
everything. Basic spell checking has been peformed. Please let me know
if  there is  anything that  would lead  to incorrect  information, or
something  is so  mangled  that  it needs  revising.  But  if you  can
basically  understand  what was  intended,  just  cope with  it.  Just
cope:-)

BTW, "110" port is  an "I/O" port that has been OCRed  badly, as is an
"1/0" port.

**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD76C30x   Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91
***Notes:...
***Info:...
***Versions:...
***Features:
o   Two fully programmable and independent serial I/O ports 
    configurable as PC/AT compatible (WD16C452) or PS/2 
    compatible (WD16C552)
    - Loopback controls for communications link fault isolation for 
      each ACE
    - Line break generation and detection for each ACE
    - Complete status reporting capabilities
    - Generation and stripping of serial asynchronous data control 
      bits (start, stop, parity)
    - Programmable baud rate generator and MODEM control signals for 
      each port
    - Programmable baud rate generator input clock
    - Optional 16 byte FIFO buffers on both transmit and receive of 
      each port for CPU relief during high speed data transfer
    - Programmable FIFO threshold levels of 1 , 4, 8, or 14 bytes on 
      each port
o   Parallel port configurable as a fully Centronics or PS/2 
    compatible, bidirectional parallel port
o   Independently programmable parallel port
o   Interrupt multiplexing logic
    - Selectable multiplexing logic for connecting PC/AT interrupt 
      request lines to the WD76C10 single chip AT controller
o   Clock generation circuitry
    - 80287 coprocessor clock generation
    - WD76C10 and floppy controller clock generation
    - 8042 keyboard clock generation
o   Built-in testability features
o   Hardware or software controllable sleep mode
o   CMOS implementation for high speed and low power requirements 
o   Pulse extension on IRQ inputs
o   84-pin PLCC and PQFP packages

**WD7615     Desktop Buffer Manager                          <04/15/92...
**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...