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**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*SIS...
**5595 Pentium PCI System I/O <12/24/97
***Notes:...
***Info:...
***Versions:...
***Features:
o Integrated PCI-to-ISA Bridge
− Translate s PCI Bus Cycles into ISA Bus Cycles.
− Translate s ISA Master or DMA Cycles into PCI Bus Cycles.
− Provide s a Dword Post Buffer for PCI to ISA Memory cycles.
− Two 32 bit Prefetch/Post Buffers Enhance the DMA and ISA
Master Performance.
− Fully Compliant to PCI 2.1.
o Supports both Desktop and Mobile Advanced Power Management Logic
− Meets ACPI 1.0 Requirements.
− Supports Both ACPI and Legacy PMU.
− Supports Suspend to RAM.
− Supports Suspend to Hard Disk.
− Optionally Tri−state ISA bus in low power state.
− Supports Battery Management and LB/LLB/AC Indicator.
− Supports CPU's SMM Mode Interface.
− Supports CPU Stop Clock.
− Supports Power Button of ACPI.
− Supports three system timers and SMI# watchdog timer.
− Supports Automatic Power Control.
− Supports Modem Ring−in, RTC Alarm Wake up.
− Supports Thermal Detection.
− Supports GPIOs, and GPOs for External Devices Control.
− Supports Programmable Chip Select.
− Supports PCI Bus Power Management Interface Spec. 1.0
− Supports Pentium II Sleep State.
o Enhanced DMA Functions
− 8-, 16- bit DMA Data Transfer.
− Two 8237A Compatible DMA Controllers with Seven Independent
Programmable Channels.
− Provide the Readability of the two 8237 Associated Registers.
− Support Distributed DMA.
− Support PC/PCI DMA.
− Per DMA channel programmable in legacy, DDMA or PC/PCI DMA mode
operation.
o Integrated Two 8259A Interrupt Controllers
− 14 Independently Programmable Channels for Level- or Edge-
triggered Interrupts.
− Provide the Readability of the two 8259A Associated Registers.
− Support Serial IRQ.
− Support the Reroutability for the PCI Interrupts.
o Three Programmable 16-bit Counters compatible with 8254
− System Timer Interrupt.
− Generate Refresh Request.
− Speaker Tone Output.
− Provide the Readability of the 8254 Associated Registers.
o Integrated Keyboard Controller
− Hardwired Logic Provides Instant Response.
− Supports PS/2 Mouse Interface.
− Supports Keyboard Password Security or Hot Key Power On
Function.
− Supports Hot Key "Sleep" Function.
− Programmable Enable and Disable for Keyboard Controller and
PS/2 Mouse.
o Integrated Real Time Clock(RTC) with 256B CMOS SRAM
− Supports ACPI Day of Month Alarm/Month Alarm.
− Supports various Power Up events, such as Button Up, Alarm Up,
Ring Up, GPIO5/PME0# Up, GPIO10/ PME1# Up, Password Security Up,
and Hotkey Up.
− Supports various Power Down Events, like Software Power-down,
Button Power-down, and ACPI S3 Power-down.
− Supports Power Supply ’98.
− Provides RTC year 2000 solution.
o Integrated Frequency Ratio Control Logic for Pentium II CPU
o Universal Serial Bus Host Controller
− Open HCI Host Controller with Root Hub.
− Two USB Ports.
− Supports Legacy Devices.
− Supports Over Current Detection.
o Integrated Hardware Monitor Logic
− Up to 5 Positive Voltage Monitoring Inputs.
− Two Fan Speed Monitoring Inputs.
− One Temperature Sensings.
− Supports thermister- or diode- temperature sensing for Pentium
II CPU.
− Threshold Comparison of all Monitored Values.
o Supports I2C Serial Bus/ SMBUS
o Supports 2MB Flash ROM Interface
o 208 pins PQFP Package
o 5V CMOS Technology
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91
***Info:...
***Versions:...
***Features:
o 84-pin PLCC and PQFP packages
o 5V supply requirement (WD76C20)
3.3V supply requirement (WD76C20LV)
o 3.0V battery backup supply for the RTC and 114 byte SRAM (WD76C20)
2.4V battery backup supply for the RTC and 114 byte SRAM
(WD76C20LV)
o Implemented in a low-power, high-performance, 1.25 micron CMOS
technology process
o Floppy Disk Controller (FDC) software transparent power-down mode
with low standby ICC current. FOC features:
- 256 tracks support
- 100% software compatible with NEC 765A
- Integrated high-performance DPLL data separator:
- 125, 250, 300, 500 Kb/sec and 1 Mb/sec data rates
- Option to select 150 Kb/sec FM and 300 Kb/sec MFM data
rates only
- Automatic Write Precompensation:
- Defeat option
- Inner track value of 125 or 187 ns pin selectable
- On chip clock generation:
- 2 TTL clock inputs, or
- Single 16 or 32 MHz crystal circuit and one TTL clock input
- Power Qualified Reset
- Enable PQR in W076C20
- Disable PQR in W076C20LV
- Host interface read/write accesses compatible with 80286
microprocessors at speeds up to 12 MHz with 0 wait states
- Direct floppy disk drive interface - no buffers needed
- 48 mA sink output drivers
- Schmitt Trigger input line receivers
- FDC direct PC XT/AT interface compatibility
- Floppy Control and Operations Registers on chip
- In PC/AT mode, provides required signal qualification to DMA
channel
- IBM BIOS compatible
- Dual-speed spindle drive support
- PS/2 type drive support
o Real Time Clock (RTC) features:
- Software compatible with Motorola MC146818A.
- Internal time base and oscillator circuitry
- Counts seconds, minutes, and hours
- Counts days of the week, date, month, and year
- Time base input for 32.768 KHz square wave
- Time base oscillator for parallel resonant crystals
- Binary or BCD representation of time, calendar, and alarm
- 12- or 24-hour clock with AM and PM in 12-hour mode
- Daylight savings time option
- Automatic leap year compensation
- Interfaced with software as 128 RAM locations
- 114 bytes at general purpose RAM
- Status bit indicates data integrity
- Bus compatible interrupt signals (IRQ)
- Three interrupts are separately software maskable and testable:
- Time-at-day alarm - once-per-second to once-per-day
- Periodic interrupt rates tram 122 us to 500 ms
- End-at-clock update cycle
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
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