[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:
The 82485 is a second-level cache controller designed to improve the
performance of Intel486 Microprocessor systems. One 82485 cache
controller supports 64K or 128K bytes of second level cache memory
that maps to the entire 4 Gigabytes of the Intel486 microprocessor
address space. The controller is completely software transparent. One
controller plus SRAMs provides a 64K or a 128K cache. External EPROM
can be cached yet remain write protected. The 82485 is fully
compatible with the Intel486 microprocessor. All Intel486 CPU bus
cycles and timings are supported.
A complete, optional second level cache controller using the 82485 is
available as the 485Turbocache Module from Intel (data sheet order
number 240722).
2.0 FUNCTIONAL DESCRIPTION
2.1 Introduction
The 82485 is a single ported, two-way set associative cache controller
designed specifically to interface with the Intel486 microprocessor.
The controller supports either a sectored configuration (two lines per
tag) or a non-sectored configuration (one line per tag). The 82485
will directly support a nonsectored 64K data cache or a 128K sectored
data cache. Both the 64K and 128K configurations are able to map the
entire 4 gigabytes of the Intel486 microprocessor address space. The
82485 interfaces directly to the Intel486 microprocessor. All Intel-
486 CPU bus cycles and timings are supported. The 82485 also supports
0 wait state processor operation when there is a cache hit and has
provisions to support invalidation cycles, BOFF# cycles, and premature
BLAST# terminations. The controller is look aside (monitors bus act-
ivity in parallel to the processor) and write through (all writes pro-
pagate to the system bus), so it supports the same cache consistency
mechanisms as the Intel486 CPU. The controller also provides a safe
method to cache ROM BIOS through the use of a write protect pin and a
write protect strapping option.
The data cache (Static RAM) resides external to the 82485. The 82485
provides all controls for the SRAMs. No external latches or tran-
ceivers are required. The 82485 output buffers support up to eight
SRAMs. A 64K cache can be designed with only five components; nine
components for a 128K cache. Two-way set associativity is provided by
dual banked SRAMs. Data parity is supported.
The 82485 can be used to design a custom second level cache
configuration. For an easier system design and higher integration, the
82485M Turbocache can be used (see data sheet order number 240722).
This module is a complete second level cache in one package. It
consists of a single 82485 cache controller and SRAM to provide a
complete 64K or 128K second level Intel486 microprocessor second level
cache.
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD7855 System controller for 80386SX <09/25/92
***Notes:...
***Info:
1.3 GENERAL DESCRIPTION
Western Digital's WD7855/LV single chip ISA System Controller is
designed for high-performance IBM PC/AT compatible platforms.
Available for desktop, portable or low voltage (LV) applications, the
WD7855/LV supports the 803868X microprocessor operating at speeds up
to 33 MHz.
The WD7855/LV incorporates seven high-performance system controller
functions which include the ISA bus interface, CPU interface, flexible
memory controller, DMA controller, interrupt controller, timers and
advanced power management. In combination with Western Digital’s
support devices, the WD7855/LV provides a highly flexible and powerful
desktop or portable platform design.
The WD7855/LV is designed to work with all variations of 80386SX
compatible microprocessors. It supports the traditional dynamic CPUs
with the industry's only Processor Power-down feature to minimize
power consumption. The WD7855/LV fully supports static microprocessors
such as the AMD Am386SXL with CPU Stop Clock, System Management
Interrupt and I/O trapping features. The WD7855/LV incorporates
special circuitry which allows for optimizing the cache performance
and maintaining cache coherency with cached CPUs such as the Cyrix
Cx4868LC.
1.3.1 Desktop Applications
The WD7855 provides a high performance solution with a flexible memory
controller architecture, including support for eight banks of two way
interleave memory and EMS 4.0 hardware. The WD7855/LV can fully
support an external look-aside cache or a combination primary and
secondary cache. This feature makes it particularly suitable for use
with cached microprocessors such as Cyrix Cx486SLC where it maintains
cache coherency via its built-in bus snooping capability. In addition,
the WD7855/LV supports Video Local Bus Interface (VLBI) for enhanced
graphics performance.
1.3.2 Portable Applications
The WD7855LV is an ideal choice because of its advanced power
management features and power saving 3.3 volt operation which delivers
long battery life in a compact footprint. This makes it a perfect
choice for laptop, notebook, pen based and palmtop computers.
The eight bank memory controller on the WD7855LV provides the user
with great flexibility in the selection of 3.3 volt DRAMs to meet
system memory requirements in low voltage platforms. The WD7855LV
memory controller supports JEDEC standard 3.3 volt DRAM in various
configurations, including the JEIDA standard 88-pin DRAM card.
The WD7855/LV can be paired with the appropriate support devices from
Western Digital to deliver the most efficient solution for any
platform. For 5 volt desktop or portable platforms, the WD7855LV can
be used with the WD76C20 Peripheral Controller and the WD76C30 I/O
Controller. Alternatively, the WD7855 can be used with the WD7615
Buffer Manager device and a generic Super I/O chip to implement a low
cost desktop platform. For 3.3 volt applications, the WD7855LV can be
used with the WD76C20ALV and WD76C30ALV, both of which incorporate
level translators (split rail operation). For subnotebook and palmtop
type applications, WD7625LV buffer manager can be added to the
WD7855LV based solution to achieve a very compact footprint.
The WD7855/LV is a fourth generation system controller device derived
from core chips with proven compatibility and design maturity in
several of the industry’s leading desktop and portable platforms.
Designed with the state of the art 0.9 micron high performance CMOS
process, the WD7855/LV family maintains architectural compatibility
with Western Digital's WD7600 and WD7700 systems logic chip sets while
incorporating many additional performance enhancements.
***Configurations:...
***Features:...
**WD7900/LP/LV System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110 System controller for 80386DX/486 <11/30/93...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved