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**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?
***Info:...
***Configurations:...
***Features:
****M1541/1542 AGP/CPU-to-PCI bridge/Memory/Cache and Buffer Ctrl.:
[The datasheet has some features shaded. These are represented below]
[by features enclosed in []. The datasheet does not explicitly state]
[these features only apply to the M1542, and are absent in the M1541.]
[However this is the most likely reason they are shaded. ]
o Supports all Socket 7 processors. Host bus at 100MHz, 83.3MHz,
75MHz, 66 MHz, 60 MHz and 50MHz at 3.3V/2.5V.
- Supports linear wrap mode for Cyrix M1 & M2
- Supports Write Allocation feature for K6
- Supports Pseudo Synchronous AGP and PCI bus access
(CPU bus 75MHz - AGP bus 60MHz, PCI bus 30MHz,
CPU bus 83.3MHz - AGP bus 66MHz, PCI bus 33MHz,
CPU bus 100MHz - AGP bus 66MHz, PCI bus 33MHz)
o Supports Pipelined-Burst SRAM/Memory Cache
- Direct mapped, 256KB/512KB/1MB
- Write-Back/Dynamic-Write-Back cache policy
- Built-in 16K*2 bit SRAM for MESI protocol to reduce cost and
enhance performance
[- Built-in 16K*10 bit SRAM for TAG data to reduce cost and ]
[ enhance performance (reserved) ]
- Cacheable memory up to 128MB with 8-bit Tag SRAM when using
512KB L2 cache, 256MB when using 256KB L2 cache.
- Cacheable memory up to 512MB with 10-bit Tag SRAM when using
512KB L2 cache, 1GB when using 256KB L2 cache
- 3-1-1-1-1-1-1-1 for Pipelined Burst SRAM/ Memory Cache at
back-to-back burst read and write cycles.
- Supports 3.3V/5V SRAMs for Tag Address.
- Supports CPU Single Read Cycle L2 Allocation.
o Supports FPM/EDO/SDRAM DRAMs
- 8 RAS Lines up to 4G Byte support
- 64-bit data path to Memory
- Symmetrical/Asymmetrical DRAMs
- 3.3V or 5V DRAMs
- No buffer needed for RASJ and CASJ and MA
- CBR and RAS-only refresh for FPM
- CBR and RAS-only refresh and Extended refresh and self refresh
for EDO
- CBR and Self refresh for SDRAM
- 32 QWORD deep merging buffer for 3-1-1-1-1-1-1-1 posted write
cycle to enhance high speed CPU burst access
- 6-3-3-3-3-3-3-3 for back-to-back FPM read page hit
5-2-2-2-2-2-2-2 for back-to-back EDO read page hit
6-1-1-1-1-1-1-1 for back-to-back SDRAM read page hit
X-2-2-2-2-2-2-2 for retired data for posted write on FPM and
EDO page-hit
X-1-1-1-1-1-1-1 for retired data for posted write SDRAM page-hit
- Supports SDRAM internal bank operation
- Enhanced DRAM page miss performance
- Supports 64, 128, 256M-bit technology of DRAMs
- Supports Programmable-strength CAS//MA buffers.
- Supports Error Checking & Correction (ECC
[ at or below 83.3 MHz only) and Parity for DRAM ]
- Supports 4 single-sided DIMMs based on x4 DRAMs
- Supports 4 single and double-sided DIMMs based on x8 and x16
DRAMs
- Supports 4 single-sided registered DIMMs based on 4 bits data
width SDRAM
o Synchronous/Pseudo Synchronous 25/30/33MHz 3.3V/5V tolerance PCI
interface
- Concurrent PCI architecture
- PCI bus arbiter: Five PCI masters and M1533/M1543 (ISA Bridge)
and AGP Master supported
- 6 DWORDs for CPU-to-PCI Memory write posted buffers
- Converts back-to-back CPU to PCI memory write to PCI burst cycle
- 80/22 DWORDs for PCI-to-DRAM Write-posted/Read-prefetching
buffers
- PCI-to-DRAM up to 133 MB/sec bandwidth (even when L1/L2 write
back)
- L1/L2 pipelined snoop ahead for PCI-to-DRAM cycle
- Supports PCI mechanism #1 only
- PCI spec. 2.1 support. (N(32/16/8)+8 rule, passive release, fair
arbitration)
- Enhanced performance for Memory-Read-Line and Memory-Read-
Multiple and Memory-write-Invalidate PCI commands.
o Enhanced Power Management
- ACPI support
- Supports PCI bus CLKRUN function
- Supports Dynamic Clock Stop
- Supports Power On Suspend
- Supports Suspend to Disk
- Supports Suspend to DRAM
- Self Refresh during Suspend
o Accelerated Graphics Port (AGP) Interface
- Supports AGP specification V1.0
- Supports up to 64 entries table look aside buffer for Graphic
Address Remapping Table (GART)
- AGP 66MHz protocol
- AGP 1X and 2X sideband address function
- 28 entries Request queue
- 32 QWORDs Read buffer
- 16 QWORDs Write buffer
o 35x35 mm 456-pin BGA package
****M1543/C PCI-to-ISA Bus Bridge with Super I/O & Fast IR:...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99...
**M6117 386SX Single Chip PC <97...
**
**Support Chips:
**M1535/D South Bridge ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
**AMD 640/645 (Pentium Based on VIA VT82C590) [some info] c97
640=VT82C595
645=VT82C586B
The Shuttle HOT-603 is the only known motherboard with the 640
chipset.
There may be another version known as the 640AGP with AGP support. It
is difficult to determine if this ever existed.
Various sources state the AMD 640 is the same as the VIA VT82C590
(VP2) chip set. However no first-hand source (datasheet, etc) has been
found. YMMV
**Later Chipsets:...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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