[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91
***Info:...
***Configurations:...
***Features:...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**FE5400 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87
***Notes:...
***Info:
****General:
The FE5400 chip set provides all necessary core logic to build a
totally integrated IBM Personal System/2 Model 50 or 60 compatible
motherboard using the 16-bit Intel 80286 Central Processing Unit
(CPU).
The FE5400 chip set is 100% hardware (register level) and software
compatible with the PS/2 Models 50 and 60. It includes the components
needed to build a PS/2 compatible motherboard including IBM’s Micro
Channel Architecture.
The FE5400 chip set consists of four devices: FE5000, FE5010, FE5020
and FE5030. They operate at CPU clock rates of up to 20 MHz or twice
as fast as the PS/2 Model 50/60’s clock rate resulting in
significantly higher performance and a natural migration/diff-
erentiation path for PS/2 compatible manufacturers.
This highly integrated chip set significantly facilitates design and
implementation of Model 50 and 60 compatible system boards that are
smaller, less noisy, consume less power and have higher performance.
Components
The FE5000 Peripheral and Control and the FE5010 DMA and Micro Channel
Control logic devices contain the equivalent functions of two Intel
8259 interrupt controllers (16 channels), a 3-channel 8254 timer and
two 8237 DMA controllers with IBM compatible extensions. They hold the
central arbitration control point logic.
In addition, the FE5000 and FE50l0 include logic for the watchdog
timer, programmable option select, coprocessor interface, system board
I/O decode, buffer controls, clock generation and Micro Channel bus
controls.
A basic memory controller is included and an Extended Setup Facility
is provided to facilitate special configurations. The FE5000 and
FE5010 are manufactured using CMOS technology.
The FE5020 Address and Data Buffer logic device contains the address
and data buffers that are used to directly interface the device to the
Micro Channel bus without external drivers. The buffers have a 24mA
drive capability.
A local bus buffer is provided that makes it easy to integrate other
peripheral controllers such as a floppy controller, serial ports, hard
disk and display controllers.
The FE5030 Memory Controller contains the logic necessary to manage
the system’s dynamic memory (DRAM). It includes a RAS/CAS DRAM address
multiplexer and a data buffer with parity checking that interfaces CPU
and DRAM. RAS/CAS control circuitry is also included.
Memory Configuration is programmable offering the designer maximum
flexibility. The chip includes extended memory support (the Lotus,
Intel and Microsoft implementation of EMS). It supports page, static
column and interleave modes. It also allows usage of 256K, 1M and 4M
DRAM devices.
Both FE5020 and FE5030 are manufactured using BiCMOS technology for
its high speed and high drive capability.
Micro Channel and DMA
The FE5400 chip set directly interfaces to the bus and meets all Micro
Channel bus timing specifications}.
Micro Channel bus timing is, however, decoupled and independent of the
CPU clock rate. This allows the processor to run at its maximum rate
and still maintain compatibility on the bus.
Arbitration logic controls and monitors the Micro Channel and local
bus arbitration functions.
A Cost Effective Design
The FE5400 chip set is cost effective because it replaces three gate
arrays plus approximately 100 additional devices. The direct result is
a smaller motherboard with lower power consumption.
Packaging
The FE5400 chip set devices are manufactured in surface mountable
l32-pin JEDEC Standard packages.
This type of packaging allows for a higher level of logic integration
resulting in an extremely reliable device that takes up less space.
****FE5000 Peripheral and Control:...
****FE5010 DMA and Micro Channel Control logic:...
****FE5020 Address and Data Buffer logic:...
****FE5030 Memory Controller:...
***Configurations:...
***Features:...
**FE6500 CPU Core Logic for PS/2 Model 70/80 Compatibles c:88...
**WD6400SX/LP CPU Core Logic for PS/2 386SX Compatibles <90...
**WD6500 CPU Core Logic for PS/2 386DX/486 Compatible <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX <11/25/91...
**WD7700/LP System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855 System controller for 80386SX <09/25/92...
**WD7900/LP/LV System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110 System controller for 80386DX/486 <11/30/93...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved