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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
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**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98
***Info:...
***Configurations:...
***Features:...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
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*Unresearched:...
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*Western Digital...
**FE3600/A/B/C  16/20MHz AT Chip set                              c:88
***Notes:...
***Info:
****General:...
****FE3001  AT CONTROL LOGIC...
****FE3010B AT PERIPHERAL CONTROL LOGIC...
****FE3021  ADDRESS BUFFER AND MEMORY CONTROLLER
The  FE3021  device  is   designed  to  reduce  chip  count,  increase
flexibility,  and provide improved  operating speed  and functionality
when used with  the FE3001, FE301O, and FE3031  devices to implement a
low cost, high performance AT compatible computer.

Chip count  is reduced  by integrating the  memory controller,  AT bus
address buffers, and I/O , Manager functions into one chip.

The memory controller is  a high performance design, with programmable
modes  of operation.  It controls  page mode  DR.A.M or  static column
DRAM.

Up to 4  banks of DRAM may be controlled. The  DRAM bank locations are
programmable  on 128K byte  boundaries. One  memory bank  allows split
addressing, so that  one portion may be placed  in conventional memory
with  the remainder  in extended  memory, with  an additional  mode to
allow copying BIOS code from ROM to RAM for faster execution.

A major function of the FE3021  is to generate chip select decodes for
peripheral  chips  on  the  system  board, for  instance,  the  floppy
controller, hard disk controller, serial, and parallel port chips. The
floppy and  hard disk chip selects  may be disabled or  may be enabled
for  either the  primary or  secondary address  decode, as  defined by
IBM.  Four programmable  chip  selects are  available, for  supporting
serial, parallel, mouse, or other types of ports.

****FE3031  AT DATA BUFFER...
***Configurations:...
***Features:...
**FE5300        CPU Core Logic for PS/2 Model 50/60 Compatibles   c:87...
**FE5400        CPU Core Logic for PS/2 Model 50/60 Compatibles   c:87...
**FE6500        CPU Core Logic for PS/2 Model 70/80 Compatibles   c:88...
**WD6400SX/LP   CPU Core Logic for PS/2 386SX Compatibles          <90...
**WD6500        CPU Core Logic for PS/2 386DX/486 Compatible       <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX         <11/25/91...
**WD7700/LP     System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855        System controller for 80386SX                <09/25/92...
**WD7900/LP/LV  System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110        System controller for 80386DX/486            <11/30/93...
**
**Support Chips:
**WD76C20x   Floppy, RTC, IDE and Support Logic Device       <11/25/91...
**WD76C30x   Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615     Desktop Buffer Manager                          <04/15/92...
**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...