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**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:...
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**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**SL82C460   'Haydn II' 80486 chipset   [no datasheet]         c:Jun91
***Notes:...
***Configurations:...
**SL82C470   'Mozart' 486/386 EISA chipset                     c:Dec91...
**SL82C490   'Wagner' 486?              [no datasheet]               ?...
**SL82C550   'Rossini' Pentium          [no datasheet]            c:95...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
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**VL82C114 Combination I/O chip                                      ?
***Info:
The  VL82C114  Combination  I/O  chip,  when  used  with  VLSI  System
Controller chips, allows designers  to implement a very cost-effective
minimum  chip  count  motherboard.   This  chip  combines  a  keyboard
controller and  a real-time clock with the  address registers/ latches
and  buffers  which  are  normally  required  in  ISA  bus  compatible
systems.  The VL82C114 features  an AT-compatible  keyboard controller
with integrated PS/2 mouse support and a 146818A-compatible real-time
clock. The  VL82C114 also has  114 additional bytes  of battery-backed
CMOS RAM for  use in extended system setup.  In addition, the VL82C114
provides support for processors with write-back cache controllers.

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