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**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
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**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98
***Info:...
***Configurations:...
***Features:...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C425 486 Cache controller ?
***Info:
The VL82C425 Cache Controller provides a low-cost direct map,
look-aside write-back cache option for use with the VL82C486 System
Controller. It supports from 64 KB to 1 MB cache sizes. It can cache
from the first 8 MB to the first 256 MB of on-board DRAM, depending on
the cache size and tag option selected. the cache line size is 16
bytes (four double words).
one or two 32-bit wide banks of asynchronous cache SRAM may be used to
hold the data. Increased read performance is obtained by using two
banks which allow interleaved accesses during burst read cycles.
only one 8-bit or 9-bit (optional) tag SRAM is required to hold the
upper memory address bits and the dirty bit. The number of tag SRAM
locations required is equal to the size of the data cache (in bytes)
divided by 16.
***Versions:...
***Features:
o Single chip second-level cache controller optimized for use with
the VL82C486 System Controller
o Look-aside architecture allows cache to be board-level option
o Write-back architecture for increased write performance
o Direct Map with external TAGs
o Up to 33Mhz operation
o Supports single motherboard designs for the following cache sizes:
- 64 KB (caches 8 or 16 MB DRAM)
- 128 KB (caches 16 or 32 MB DRAM)
- 256 KB (caches 32 or 64 MB DRAM)
- 512 KB (caches 64 or 128 MB DRAM)
- 1 MB (caches 128 or 256 MB DRAM)
o Low total cache system cost:
- Uses commodity SRAMs for Cache Tag and Cache Data
- 25 ns data SRAMs; 20 ns tag SRAMs at 33 MHz
o High Performance:
- 2-1-1-1 Burst Mode read cycles with two banks of data SRAM
- 2-2-2-2 Burst Mode read cycles with now bank of data SRAM
- One wait state writes on cache-hits
- Minimum cache-miss penalty
o Flexibility:
- Supports 8-bit or 9-bit TAG RAM (inclusive of DIRTY bit)
- Supports one or two banks of SRAM
o Maintains full coherency during DMA/Master Mode Cycles
- The VL82C425 is transparent to software, acting as a front-end
to system DRAM
o Setup/sizing mode provides direct access to cache SRAMs
o 128-lead metric quad flat pack (MQFP)
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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